[coreboot-gerrit] Patch set updated for coreboot: soc/intel: Add MSR to support enabling turbo frequency
Shaunak Saha (shaunak.saha@intel.com)
gerrit at coreboot.org
Wed Nov 2 20:08:23 CET 2016
Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17211
-gerrit
commit e064a13fc19b5f2eeec4d210080af2b4a0336943
Author: Shaunak Saha <shaunak.saha at intel.com>
Date: Wed Nov 2 10:52:23 2016 -0700
soc/intel: Add MSR to support enabling turbo frequency
This patch adds definition for IA32_PERF_CTL and
FREQ_LIMIT_RATIO MSR's. FREQ_LIMIT_RATIO register
allows determines the ratio limits to be used to
limit frequency. PERF_CTL is Performance Control MSR.
BIOS makes request for a new Performance state (P-state)
by writing this MSR.
BUG=chrome-os-partner:58158
BRANCH=None
Change-Id: I50a792accbaab1bff313fd00574814d7dbba1f6b
Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
src/include/cpu/intel/turbo.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h
index 6626cb1..cfa859a 100644
--- a/src/include/cpu/intel/turbo.h
+++ b/src/include/cpu/intel/turbo.h
@@ -26,6 +26,9 @@
#define H_MISC_DISABLE_TURBO (1 << 6)
+#define IA32_PERL_CTL 0x199
+#define FREQ_LIMIT_RATIO 0x1AD
+
enum {
TURBO_UNKNOWN,
TURBO_UNAVAILABLE,
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