[coreboot-gerrit] Patch merged into coreboot/master: northbridge/amd: Modify 00670F00 chip.h to match DCT

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit c56a558c18c7599d37a0f119b0a51c46cf274c32
Author: Marshall Dawson <marshalldawson3rd at gmail.com>
Date:   Sat Oct 8 09:12:27 2016 -0600

    northbridge/amd: Modify 00670F00 chip.h to match DCT
    
    The Stoney device supports only a single channel of DRAM with
    two DIMMs.  Correct the dimmensions of the SPD lookup array.
    
    Original-Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
    Original-Reviewed-by: <marcj303 at gmail.com>
    (cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8)
    
    Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
    Reviewed-on: https://review.coreboot.org/17145
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See https://review.coreboot.org/17145 for details.

-gerrit