[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Skip FSP initiated core/MP init

[Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri@intel.com)]

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17201

-gerrit

commit bb8088865f2b16b84e9f1247af4b1c7e044cc005
Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
Date:   Mon Oct 31 17:15:30 2016 -0700

    soc/intel/apollolake: Skip FSP initiated core/MP init
    
    Enable skip FSP initiated core/MP init as it is
    implemented in coreboot.
    
    BUG=chrome-os-partner:56922
    BRANCH=None
    
    Change-Id: I9417dab3135ca1e0104fc3bde63518288bcfa76a
    Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
---
 src/soc/intel/apollolake/chip.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 181d4d6..12aea77 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -465,6 +465,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 	/* Disable monitor mwait since it is broken due to a hardware bug without a fix */
 	silconfig->MonitorMwaitEnable = 0;
 
+	silconfig->SkipMpInit = 1;
+
 	/* Disable setting of EISS bit in FSP. */
 	silconfig->SpiEiss = 0;