[coreboot-gerrit] Patch merged into coreboot/master: commonlib/lz4: Avoid unaligned memory access on RISC-V

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 4acb0e774220c0705a71689b6620c976297d417c
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date:   Fri May 27 09:05:02 2016 +0200

    commonlib/lz4: Avoid unaligned memory access on RISC-V
    
    From the User-Level ISA Specification v2.0:
    
       "We do not mandate atomicity for misaligned accesses so simple
        implementations can just use a machine trap and software handler to
        handle misaligned accesses." (— http://riscv.org/specifications/)
    
    Spike traps on unaligned accesses.
    
    Change-Id: Ia57786916f4076cc08513f4e331c2deec9cfa785
    Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
    Reviewed-on: https://review.coreboot.org/14983
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/14983 for details.

-gerrit