[coreboot-gerrit] Patch set updated for coreboot: [DO NOT MERGE] Add new RISC-V HTIF console driver

[Jonathan Neuschäfer (j.neuschaefer@gmx.net)]

Jonathan Neuschäfer (j.neuschaefer at gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14982

-gerrit

commit 369a9244b74bb876ce737019ece9a9c7fb5694c6
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date:   Fri May 27 09:05:02 2016 +0200

    [DO NOT MERGE] Add new RISC-V HTIF console driver
    
    The HTIF is already deprecated and has been removed in newer versions of
    Spike. In the older Spike 3bfc00ef this driver works.
    
    Maybe src/drivers/emulation/riscv would be a better place.
    
    Change-Id: I8b25829e8cc17ec9604c6e1391a2f96eefe71d07
    Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
 src/drivers/uart/Kconfig      |  9 ++++++
 src/drivers/uart/Makefile.inc |  7 ++++
 src/drivers/uart/htif.c       | 75 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 91 insertions(+)

diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig
index 4faa48d..12514b9 100644
--- a/src/drivers/uart/Kconfig
+++ b/src/drivers/uart/Kconfig
@@ -73,3 +73,12 @@ config UART_PCI_ADDR
 	  * Bus << 20
 	  * Device << 15
 	  * Function << 12
+
+config DRIVERS_UART_HTIF
+	bool "RISC-V HTIF console"
+	default n
+	depends on ARCH_RISCV
+	help
+	  Support for the console part of the RISC-V Host-Target Interface.
+
+	  Currently, only output is implemented.
diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc
index 4b2aa53..232e80a 100644
--- a/src/drivers/uart/Makefile.inc
+++ b/src/drivers/uart/Makefile.inc
@@ -36,4 +36,11 @@ romstage-y += pl011.c
 ramstage-y += pl011.c
 endif
 
+ifeq ($(CONFIG_DRIVERS_UART_HTIF),y)
+bootblock-y += htif.c
+verstage-y += htif.c
+romstage-y += htif.c
+ramstage-y += htif.c
+endif
+
 endif
diff --git a/src/drivers/uart/htif.c b/src/drivers/uart/htif.c
new file mode 100644
index 0000000..7533981
--- /dev/null
+++ b/src/drivers/uart/htif.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Jonathan Neuschäfer <j.neuschaefer at gmx.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/encoding.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <console/uart.h>
+#include <delay.h>
+#include <device/device.h>
+#include <rules.h>
+#include <spike_util.h>
+#include <stdint.h>
+
+/* Driver for console output over RISC-V's Host-Target Interface (HTIF) */
+
+uintptr_t uart_platform_base(int idx)
+{
+	if (idx == 0)
+		return CSR_MTOHOST;
+	return 0;
+}
+
+void uart_init(int idx)
+{
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+	if (idx != 0)
+		return;
+
+	/* Device 1: console; command 1: write */
+	write_csr(mtohost, TOHOST_CMD(1, 1, data));
+
+	/* Read from mfromhost to avoid some kind of race condition when
+	 * characters are printed to fast */
+	read_csr(mfromhost);
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+	// not yet implemented
+	return 0;
+}
+
+void uart_tx_flush(int idx)
+{
+}
+
+#if ENV_RAMSTAGE
+void uart_fill_lb(void *data)
+{
+	/* bogus: */
+	struct lb_serial serial;
+	serial.type = LB_SERIAL_TYPE_IO_MAPPED;
+	serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+	serial.baud = default_baudrate();
+	serial.regwidth = sizeof(uint8_t);
+	lb_add_serial(&serial, data);
+
+	lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif