[coreboot-gerrit] Patch set updated for coreboot: mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14892

-gerrit

commit da81b4886fecb38f1d6b50292cdfe67e33749893
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Wed May 18 13:33:13 2016 -0500

    mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header
    
    The ASUS KGPE-D16/KCMA-D8 have an on-board header for a second RS-232
    serial port, however it is disabled by default due to the SuperIO
    default pin mux settings.  Enable the secondary serial port early
    in romstage to allow use for coreboot console if desired.
    
    Change-Id: I5b83659dd8b0d6af559c9ceccee55c4cc2f17165
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/mainboard/asus/kcma-d8/dsdt.asl    | 24 ++++++++++++++++++++++++
 src/mainboard/asus/kcma-d8/romstage.c  |  8 ++++++--
 src/mainboard/asus/kgpe-d16/dsdt.asl   | 24 ++++++++++++++++++++++++
 src/mainboard/asus/kgpe-d16/romstage.c |  8 ++++++--
 4 files changed, 60 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl
index ef87d31..d305af5 100644
--- a/src/mainboard/asus/kcma-d8/dsdt.asl
+++ b/src/mainboard/asus/kcma-d8/dsdt.asl
@@ -587,6 +587,30 @@ DefinitionBlock (
 						})
 					}
 				}
+
+				/* UART 2 */
+				Device (URT2)
+				{
+					Name (_HID, EisaId ("PNP0501"))		// "PNP0501" for UART
+					Name(_PRW, Package () {0x03, 0x04})	// Wake from S1-S4
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)			// Always enable
+					}
+					Name (_PRS, ResourceTemplate() {
+						StartDependentFn(0, 1) {
+							IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+							IRQNoFlags() { 3 }
+						} EndDependentFn()
+					})
+					Method (_CRS, 0)
+					{
+						Return(ResourceTemplate() {
+							IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+							IRQNoFlags() { 3 }
+						})
+					}
+				}
 			}
 
 			/* High Precision Event Timer */
diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c
index 9d1d95f..a9d647c 100644
--- a/src/mainboard/asus/kcma-d8/romstage.c
+++ b/src/mainboard/asus/kcma-d8/romstage.c
@@ -46,7 +46,8 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
-#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
+#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
+#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
 
 static void activate_spd_rom(const struct mem_controller *ctrl);
 
@@ -401,9 +402,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		sb7xx_51xx_pci_port80();
 
 		/* Initialize early serial */
-		winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+		winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE);
 		console_init();
 
+		/* Configure secondary serial port pin mux */
+		winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B);
+
 		/* Disable LPC legacy DMA support to prevent lockup */
 		byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78);
 		byte &= ~(1 << 0);
diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl
index 5f9195a..d364f1f 100644
--- a/src/mainboard/asus/kgpe-d16/dsdt.asl
+++ b/src/mainboard/asus/kgpe-d16/dsdt.asl
@@ -587,6 +587,30 @@ DefinitionBlock (
 						})
 					}
 				}
+
+				/* UART 2 */
+				Device (URT2)
+				{
+					Name (_HID, EisaId ("PNP0501"))		// "PNP0501" for UART
+					Name(_PRW, Package () {0x03, 0x04})	// Wake from S1-S4
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)			// Always enable
+					}
+					Name (_PRS, ResourceTemplate() {
+						StartDependentFn(0, 1) {
+							IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+							IRQNoFlags() { 3 }
+						} EndDependentFn()
+					})
+					Method (_CRS, 0)
+					{
+						Return(ResourceTemplate() {
+							IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+							IRQNoFlags() { 3 }
+						})
+					}
+				}
 			}
 
 			/* High Precision Event Timer */
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 5a7400e..1ff1ed3 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -46,7 +46,8 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
-#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
+#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
+#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
 
 static void activate_spd_rom(const struct mem_controller *ctrl);
 
@@ -442,9 +443,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		sb7xx_51xx_pci_port80();
 
 		/* Initialize early serial */
-		winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+		winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE);
 		console_init();
 
+		/* Configure secondary serial port pin mux */
+		winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B);
+
 		/* Disable LPC legacy DMA support to prevent lockup */
 		byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78);
 		byte &= ~(1 << 0);