[coreboot-gerrit] Patch merged into coreboot/master: drivers/intel/fsp2_0: Send post codes around calls to the blobs

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit c4ea8f7d3fb56b43482b8abd8405280f50d98864
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date:   Mon May 23 12:16:58 2016 -0700

    drivers/intel/fsp2_0: Send post codes around calls to the blobs
    
    By design, FSP will send POST codes to port 80. In this case we have
    both coreboot and FSP pushing post codes, which may make debugging
    harder. In order to get a clear picture of where FSP execution begins
    and ends, send post codes before and after any call to the FSP blobs.
    
    Note that sending a post code both before and after is mostly useful
    on chromeec enabled boards, where the EC console will provide a
    historic list of post codes.
    
    Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
    Reviewed-on: https://review.coreboot.org/14951
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See https://review.coreboot.org/14951 for details.

-gerrit