[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: enable RTC
Jagadish Krishnamoorthy (jagadish.krishnamoorthy@intel.com)
gerrit at coreboot.org
Wed May 25 03:43:12 CEST 2016
Jagadish Krishnamoorthy (jagadish.krishnamoorthy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14883
-gerrit
commit c7d6803868031fa9f23e2f8b478aa14815cf0262
Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Date: Tue May 17 18:06:49 2016 -0700
soc/intel/apollolake: enable RTC
BUG=none
TEST=Boot to OS and verfiy if rtc0 device is created
under /sys/class/rtc/
Change-Id: Idec569255859816fda467bb42a215c00f7c0e16e
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
---
src/soc/intel/apollolake/lpc.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 48dfb1f..9d4b6c0 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -15,13 +15,17 @@
* GNU General Public License for more details.
*/
+#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
#include <soc/acpi.h>
#include <soc/lpc.h>
#include <soc/pci_ids.h>
+#include <soc/pm.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "chip.h"
@@ -43,6 +47,27 @@
* opens up IO and memory windows as needed.
*/
+static void rtc_init(void)
+{
+ uint32_t gen_pmcon1;
+ int rtc_fail;
+ const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+
+ if (!ps) {
+ printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n");
+ return;
+ }
+
+ gen_pmcon1 = ps->gen_pmcon1;
+ rtc_fail = !!(gen_pmcon1 & RPS);
+ /* Ensure the date is set including century byte. */
+ cmos_check_update_date();
+ if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS))
+ init_vbnv_cmos(rtc_fail);
+ else
+ cmos_init(rtc_fail);
+}
+
static void lpc_init(struct device *dev)
{
uint8_t scnt;
@@ -61,6 +86,9 @@ static void lpc_init(struct device *dev)
else if (cfg->serirq_mode == SERIRQ_CONTINUOUS)
scnt |= SCNT_EN | SCNT_MODE;
pci_write_config8(dev, REG_SERIRQ_CTL, scnt);
+
+ /* Initialize RTC */
+ rtc_init();
}
static void soc_lpc_add_io_resources(device_t dev)
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