[coreboot-gerrit] New patch to review for coreboot: AMD/spi: Do not reset fifo after skipping the sent bytes

[Zheng Bao (fishbaozi@gmail.com)]

Zheng Bao (fishbaozi at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14955

-gerrit

commit b7aca4f371004e80ee7d6d2d5f899686a6791746
Author: zbao <fishbaozi at gmail.com>
Date:   Tue May 24 21:21:26 2016 +0800

    AMD/spi: Do not reset fifo after skipping the sent bytes
    
    After we skip the bytes we send, the fifo pointer is at
    right position. Reseting the fifo will change it to a
    wrong place.
    
    Please view the flashrom code, which tells the same thing.
    https://code.coreboot.org/p/flashrom/source/tree/HEAD/trunk/sb600spi.c#L257
    
    Change-Id: I31d487ce32c0d7ca3dead36d2b14611e73b1ad60
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/southbridge/amd/agesa/hudson/spi.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index e8ab372..31160bd 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -143,7 +143,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
 		cmd = spi_read(SPI_REG_FIFO);
 	}
 
-	reset_internal_fifo_pointer();
 	for (count = 0; count < bytesin; count++, din++) {
 		*(uint8_t *)din = spi_read(SPI_REG_FIFO);
 	}