[coreboot-gerrit] Patch set updated for coreboot: mb/gigabyte/ga-g41m-es2l: Use x4x_late_init()

[Damien Zammit (damien@zamaudio.com)]

Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14926

-gerrit

commit 26262b2e7085fa4d8201e2519fead0dec9237d2f
Author: Damien Zammit <damien at zamaudio.com>
Date:   Sat May 21 01:56:53 2016 +1000

    mb/gigabyte/ga-g41m-es2l: Use x4x_late_init()
    
    This patch adds DMI/EP init to the board and fixes
    a couple of minor things.
    
    Change-Id: I10d0f6ce747b60499680e4dc229b7fcbb16cc039
    Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
 src/mainboard/gigabyte/ga-g41m-es2l/Kconfig    |  3 +++
 src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 29 +++++++++++++++++++++-----
 2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
index 0a26f83..31b29bb 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
@@ -26,6 +26,9 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_1024
 	select INTEL_EDID
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select PCIEXP_ASPM
+	select PCIEXP_CLK_PM
+	select PCIEXP_L1_SUB_STATE
 
 config MMCONF_BASE_ADDRESS
 	hex
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index bff481f..6365404 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -50,9 +50,10 @@ static void mb_gpio_init(void)
 	pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
 	pci_write_config8(dev, GPIO_CNTL, 0x10);
 
-	outl(0x1f15f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+	outl(0x1f35f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
 	outl(0xe2e9ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
-	outl(0xe0d7fcc3, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+	outl(0xe0d7ec02, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+	outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
 	outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
 	outl(0x000000e7, DEFAULT_GPIOBASE + 0x30);
 	outl(0x000000f0, DEFAULT_GPIOBASE + 0x34);
@@ -66,9 +67,9 @@ static void mb_gpio_init(void)
 	ite_reg_write(GPIO_DEV, 0x29, 0x0a);
 	ite_reg_write(GPIO_DEV, 0x2c, 0x01);
 	ite_reg_write(GPIO_DEV, 0x62, 0x08);
-	ite_reg_write(GPIO_DEV, 0x62, 0x08);
 	ite_reg_write(GPIO_DEV, 0x72, 0x00);
 	ite_reg_write(GPIO_DEV, 0x73, 0x00);
+	ite_reg_write(GPIO_DEV, 0xb8, 0x00);
 	ite_reg_write(GPIO_DEV, 0xbb, 0x40);
 	ite_reg_write(GPIO_DEV, 0xc0, 0x00);
 	ite_reg_write(GPIO_DEV, 0xc1, 0xc7);
@@ -89,6 +90,7 @@ static void mb_gpio_init(void)
 	ite_reg_write(EC_DEV, 0xf2, 0x0a);
 	ite_reg_write(EC_DEV, 0xf3, 0x80);
 	ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
+	ite_reg_write(EC_DEV, 0x30, 0x01); // Enable
 
 	/* IRQ routing */
 	RCBA32(0x3100) = 0x00002210;
@@ -98,10 +100,23 @@ static void mb_gpio_init(void)
 	RCBA32(0x3110) = 0x00000001;
 	RCBA32(0x3140) = 0x00410032;
 	RCBA32(0x3144) = 0x32100237;
+	RCBA32(0x3148) = 0x00000000;
 
 	/* Enable IOAPIC */
 	RCBA8(0x31ff) = 0x03;
 	RCBA8(0x31ff);
+
+	RCBA32(0x3410) = 0x00190464;
+	RCBA32(0x3418) = 0x003c0063;
+	RCBA32(0x341c) = 0x00000000;
+	RCBA32(0x3430) = 0x00000001;
+	RCBA32(0x3e00) = 0xff000001;
+	RCBA32(0x3e08) = 0x00000080;
+	RCBA32(0x3e0c) = 0x00800000;
+	RCBA32(0x3e40) = 0xff000001;
+	RCBA32(0x3e48) = 0x00000080;
+	RCBA32(0x3e4c) = 0x00800000;
+	RCBA32(0x3f00) = 0x0000000b;
 }
 
 static void ich7_enable_lpc(void)
@@ -126,9 +141,8 @@ void main(unsigned long bist)
 	RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
 
 	/* Set southbridge and Super I/O GPIOs. */
-	mb_gpio_init();
-
 	ich7_enable_lpc();
+	mb_gpio_init();
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	/* Disable SIO reboot */
@@ -146,4 +160,9 @@ void main(unsigned long bist)
 	quick_ram_check();
 	cbmem_initialize_empty();
 	printk(BIOS_DEBUG, "Memory initialized\n");
+
+	x4x_late_init();
+
+	printk(BIOS_DEBUG, "x4x late init complete\n");
+
 }