[coreboot-gerrit] Patch set updated for coreboot: soc/intel/quark: Rename usb.c to ehci.c
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Mon May 23 02:25:32 CEST 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14939
-gerrit
commit 02d7d5f685a4444f9344fa1964524800d0eac8b6
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sun May 22 09:01:41 2016 -0700
soc/intel/quark: Rename usb.c to ehci.c
Rename usb.c to ehci.c since it contains EHCI specific content.
TEST=Build and run on Galileo Gen2
Change-Id: Ifdb7cd937b1dffda1959b76e1c911ffd93f53cb6
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/soc/intel/quark/Makefile.inc | 2 +-
src/soc/intel/quark/ehci.c | 92 ++++++++++++++++++++++++++++++++++++++++
src/soc/intel/quark/usb.c | 92 ----------------------------------------
3 files changed, 93 insertions(+), 93 deletions(-)
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index b63e613..a6d03b1 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -25,6 +25,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-y += chip.c
+ramstage-y += ehci.c
ramstage-y += gpio_i2c.c
ramstage-y += memmap.c
ramstage-y += northcluster.c
@@ -33,7 +34,6 @@ ramstage-y += reg_access.c
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
-ramstage-y += usb.c
CPPFLAGS_common += -I$(src)/soc/intel/quark
CPPFLAGS_common += -I$(src)/soc/intel/quark/include
diff --git a/src/soc/intel/quark/ehci.c b/src/soc/intel/quark/ehci.c
new file mode 100644
index 0000000..460ef23
--- /dev/null
+++ b/src/soc/intel/quark/ehci.c
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <soc/pci_devs.h>
+#include <soc/reg_access.h>
+
+/* USB Phy Registers */
+#define USB2_GLOBAL_PORT 0x4001
+#define USB2_PLL1 0x7F02
+#define USB2_PLL2 0x7F03
+#define USB2_COMPBG 0x7F04
+
+/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL
+ * reference clock and Port2 as a USB device port, the following sequence must
+ * be followed
+ */
+static const struct reg_script init_script[] = {
+
+ /* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.
+ * For port 0 & 1 as host and port 2 as device.
+ */
+ REG_USB_RXW(USB2_GLOBAL_PORT, ~(BIT8 | BIT7 | BIT1), (BIT8 | BIT7)),
+
+ /*
+ * Sighting #4930653 Required BIOS change on Disconnect vref to change
+ * to 600mV.
+ */
+ REG_USB_RXW(USB2_COMPBG, ~(BIT10 | BIT9 | BIT8 | BIT7),
+ (BIT10 | BIT7)),
+
+ /* Sideband register write to USB AFE (Phy)
+ * (pllbypass) to bypass/Disable PLL before switch
+ */
+ REG_USB_OR(USB2_PLL2, BIT29),
+
+ /* Sideband register write to USB AFE (Phy)
+ * (coreclksel) to select 120MHz (ickusbcoreclk) clk source.
+ * (Default 0 to select 96MHz (ickusbclk96_npad/ppad))
+ */
+ REG_USB_OR(USB2_PLL1, BIT1),
+
+ /* Sideband register write to USB AFE (Phy)
+ * (divide by 8) to achieve internal 480MHz clock
+ * for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz)
+ */
+ REG_USB_RXW(USB2_PLL1, ~(BIT6 | BIT5 | BIT4 | BIT3), BIT6),
+
+ /* Sideband register write to USB AFE (Phy)
+ * Clear (pllbypass)
+ */
+ REG_USB_AND(USB2_PLL2, ~BIT29),
+
+ /* Sideband register write to USB AFE (Phy)
+ * Set (startlock) to force the PLL FSM to restart the lock
+ * sequence due to input clock/freq switch.
+ */
+ REG_USB_OR(USB2_PLL2, BIT24),
+ REG_SCRIPT_END
+};
+
+static void init(device_t dev)
+{
+ printk(BIOS_INFO, "Initializing USB PLLs\n");
+ reg_script_run_on_dev(dev, init_script);
+}
+
+static struct device_operations device_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = init,
+};
+
+static const struct pci_driver driver __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = EHCI_DEVID,
+};
diff --git a/src/soc/intel/quark/usb.c b/src/soc/intel/quark/usb.c
deleted file mode 100644
index 460ef23..0000000
--- a/src/soc/intel/quark/usb.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci_ids.h>
-#include <soc/pci_devs.h>
-#include <soc/reg_access.h>
-
-/* USB Phy Registers */
-#define USB2_GLOBAL_PORT 0x4001
-#define USB2_PLL1 0x7F02
-#define USB2_PLL2 0x7F03
-#define USB2_COMPBG 0x7F04
-
-/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL
- * reference clock and Port2 as a USB device port, the following sequence must
- * be followed
- */
-static const struct reg_script init_script[] = {
-
- /* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.
- * For port 0 & 1 as host and port 2 as device.
- */
- REG_USB_RXW(USB2_GLOBAL_PORT, ~(BIT8 | BIT7 | BIT1), (BIT8 | BIT7)),
-
- /*
- * Sighting #4930653 Required BIOS change on Disconnect vref to change
- * to 600mV.
- */
- REG_USB_RXW(USB2_COMPBG, ~(BIT10 | BIT9 | BIT8 | BIT7),
- (BIT10 | BIT7)),
-
- /* Sideband register write to USB AFE (Phy)
- * (pllbypass) to bypass/Disable PLL before switch
- */
- REG_USB_OR(USB2_PLL2, BIT29),
-
- /* Sideband register write to USB AFE (Phy)
- * (coreclksel) to select 120MHz (ickusbcoreclk) clk source.
- * (Default 0 to select 96MHz (ickusbclk96_npad/ppad))
- */
- REG_USB_OR(USB2_PLL1, BIT1),
-
- /* Sideband register write to USB AFE (Phy)
- * (divide by 8) to achieve internal 480MHz clock
- * for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz)
- */
- REG_USB_RXW(USB2_PLL1, ~(BIT6 | BIT5 | BIT4 | BIT3), BIT6),
-
- /* Sideband register write to USB AFE (Phy)
- * Clear (pllbypass)
- */
- REG_USB_AND(USB2_PLL2, ~BIT29),
-
- /* Sideband register write to USB AFE (Phy)
- * Set (startlock) to force the PLL FSM to restart the lock
- * sequence due to input clock/freq switch.
- */
- REG_USB_OR(USB2_PLL2, BIT24),
- REG_SCRIPT_END
-};
-
-static void init(device_t dev)
-{
- printk(BIOS_INFO, "Initializing USB PLLs\n");
- reg_script_run_on_dev(dev, init_script);
-}
-
-static struct device_operations device_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = init,
-};
-
-static const struct pci_driver driver __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = EHCI_DEVID,
-};
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