[coreboot-gerrit] New patch to review for coreboot: soc/intel/quark: Add USB device port support

[Leroy P Leahy (leroy.p.leahy@intel.com)]

Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14942

-gerrit

commit b545e56622763112990404546d68934c90f8d47a
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Sun May 22 10:05:23 2016 -0700

    soc/intel/quark: Add USB device port support
    
    Move the USB device port errata from FSP into coreboot.
    
    TEST=Build and run on Galileo Gen2
    
    Change-Id: Ic79acab7a67b6670df1ab79a50c41bf8b1889cc8
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/soc/intel/quark/ehci.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/intel/quark/ehci.c b/src/soc/intel/quark/ehci.c
index 8e534a5..2524fa7 100644
--- a/src/soc/intel/quark/ehci.c
+++ b/src/soc/intel/quark/ehci.c
@@ -28,6 +28,12 @@
 #define EHCI_OUT_THRESHOLD_VALUE        0x7f
 #define EHCI_IN_THRESHOLD_VALUE         0x7f
 
+/* Platform init USB device interrupt masks */
+#define V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG    (0x0000007f)
+#define V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG   \
+	(B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK \
+	| B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK)
+
 /* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL
  * reference clock and Port2 as a USB device port, the following sequence must
  * be followed