[coreboot-gerrit] New patch to review for coreboot: soc/intel/quark: Switch reference from uart_dev to uart_bdf

[Leroy P Leahy (leroy.p.leahy@intel.com)]

Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14938

-gerrit

commit 69a662cad583b838ea3f07e7e3512e708b0fe117
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Sun May 22 07:50:27 2016 -0700

    soc/intel/quark: Switch reference from uart_dev to uart_bdf
    
    Switch from using uart_dev to uart_bdf to better describe the value
    in use.
    
    TEST=Build and run on Galileo Gen2
    
    Change-Id: If5066b93ea8ccce4a5b89ee3984c7413d5358e71
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/soc/intel/quark/romstage/uart.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c
index 2d53a48..9e8f6c5 100644
--- a/src/soc/intel/quark/romstage/uart.c
+++ b/src/soc/intel/quark/romstage/uart.c
@@ -28,15 +28,15 @@ int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base)
 	uint16_t reg16;
 
 	/* HSUART controller #1 (B0:D20:F5). */
-	device_t uart_dev = PCI_DEV(bus, dev, func);
+	pci_devfn_t uart_bdf = PCI_DEV(bus, dev, func);
 
 	/* Decode BAR0(offset 0x10). */
-	pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base);
+	pci_write_config32(uart_bdf, PCI_BASE_ADDRESS_0, mmio_base);
 
 	/* Enable MEMBASE at CMD(offset 0x04). */
-	reg16 = pci_read_config16(uart_dev, PCI_COMMAND);
+	reg16 = pci_read_config16(uart_bdf, PCI_COMMAND);
 	reg16 |= PCI_COMMAND_MEMORY;
-	pci_write_config16(uart_dev, PCI_COMMAND, reg16);
+	pci_write_config16(uart_bdf, PCI_COMMAND, reg16);
 
 	return 0;
 }