[coreboot-gerrit] Patch set updated for coreboot: Coreboot: Jazz: Add PMIC initialization
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Fri May 20 18:24:16 CEST 2016
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14916
-gerrit
commit ca8868b2081f7f41e200b191bbf78c6de10d28da
Author: Akshay Saraswat <akshay.s at samsung.com>
Date: Mon Aug 11 20:24:11 2014 +0530
Coreboot: Jazz: Add PMIC initialization
Adding initial PMIC setup using I2C for Exynos7 in this patch.
BUG=None
BRANCH=None
TEST=Tested by checking the power of the IPs. UART will not
unless it gets power from this PMIC.
Change-Id: I4f23d6e636e1620402fc19693c56abefa0bf36b7
Signed-off-by: Akshay Saraswat <akshay.s at samsung.com>
---
src/mainboard/samsung/jazz/romstage.c | 57 ++++++++++++-
src/mainboard/samsung/jazz/s2mps15.h | 155 ++++++++++++++++++++++++++++++++++
2 files changed, 211 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/samsung/jazz/romstage.c b/src/mainboard/samsung/jazz/romstage.c
index 7c714ac..43f2941 100644
--- a/src/mainboard/samsung/jazz/romstage.c
+++ b/src/mainboard/samsung/jazz/romstage.c
@@ -28,11 +28,66 @@
#include <soc/gpio.h>
#include <soc/i2c.h>
#include <soc/periph.h>
+#include <soc/pinmux.h>
#include <soc/power.h>
+#include "s2mps15.h"
+
+#define PMIC_I2C_BUS 4
+
+struct pmic_write
+{
+ int or_orig; /* Whether to or in the original value */
+ uint8_t reg; /* Register to write */
+ uint8_t val; /* Value to write */
+};
+
+/*
+ * Use read-modify-write for S2MPS15 control registers and clobber the
+ * output voltage setting (BUCK?DVS?) registers.
+ */
+struct pmic_write pmic_writes[] =
+{
+ { (PM_VDD_AP >= 1000 ? 0 : 1), S2MPS15_REG_LDO_DVS1,
+ (PM_VDD_AP >= 1000 ? 0x84 : 0x0) },
+ { 0, S2MPS15_REG_LDO_DVS2, 0x84 },
+ { 0, S2MPS15_REG_LDO_DVS3, 0x84 },
+ { 0, S2MPS15_REG_LDO_DVS4, 0x84 },
+ { 0, S2MPS15_REG_BUCK1_OUT, WR_BUCK_VOLT(PM_VDD_MIF) },
+ { 0, S2MPS15_REG_BUCK2_OUT, WR_BUCK_VOLT(PM_VDD_AP) },
+ { 0, S2MPS15_REG_BUCK4_OUT, WR_BUCK_VOLT(PM_VDD_INT) },
+ { 0, S2MPS15_REG_BUCK5_OUT, WR_BUCK_VOLT(PM_VDD_DISP) },
+ { 0, S2MPS15_REG_BUCK6_OUT, WR_BUCK_VOLT(PM_VDD_G3D) },
+ { 1, S2MPS15_REG_RTC_BUF,
+ (LOW_JITTER_EN | BT_32KHZ_EN | CP_32KHZ_EN | AP_32KHZ_EN) },
+ { 1, S2MPS15_REG_WRSTBI_CTRL, WRSTBI_EN },
+ { 1, S2MPS15_REG_LDO3_CTRL, OUTPUT_PWREN_ON },
+ { 1, S2MPS15_REG_LDO14_CTRL, OUTPUT_PWREN_ON },
+ { 1, S2MPS15_REG_LDO15_CTRL, OUTPUT_PWREN_ON },
+ { 1, S2MPS15_REG_LDO17_CTRL, OUTPUT_PWREN_ON },
+};
+
static int setup_power(void)
{
- return 0;
+ int error = 0;
+ int i;
+
+ /* Initialize I2C bus to configure PMIC. */
+ exynos_pinmux_i2c4();
+ i2c_init(PMIC_I2C_BUS, 400000, 0x00); /* 400KHz */
+
+ for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) {
+ uint8_t data = 0;
+ uint8_t reg = pmic_writes[i].reg;
+
+ if (pmic_writes[i].or_orig)
+ error |= i2c_read(PMIC_I2C_BUS,
+ S2MPS15_I2C_ADDR, reg, 1, &data, 1);
+ data |= pmic_writes[i].val;
+ error |= i2c_write(PMIC_I2C_BUS, S2MPS15_I2C_ADDR, reg, 1, &data, 1);
+ }
+
+ return error;
}
void main(void)
diff --git a/src/mainboard/samsung/jazz/s2mps15.h b/src/mainboard/samsung/jazz/s2mps15.h
new file mode 100644
index 0000000..ca15d5b
--- /dev/null
+++ b/src/mainboard/samsung/jazz/s2mps15.h
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __S2MPS15_H_
+#define __S2MPS15_H_
+
+enum {
+ S2MPS15_REG_ID = 0x0,
+ S2MPS15_REG_INT1,
+ S2MPS15_REG_INT2,
+ S2MPS15_REG_INT3,
+ S2MPS15_REG_INT1MSK,
+ S2MPS15_REG_INT2MSK,
+ S2MPS15_REG_INT3MSK,
+
+ S2MPS15_REG_STATUS1,
+ S2MPS15_REG_STATUS2,
+
+ S2MPS15_REG_PWRONSRC,
+ S2MPS15_REG_OFFSRC = 0xA,
+ S2MPS15_REG_BU_CHG,
+ S2MPS15_REG_RTC_BUF,
+ S2MPS15_REG_CTRL1,
+ S2MPS15_REG_CTRL2 = 0xE,
+
+ S2MPS15_REG_RSVD1,
+ S2MPS15_REG_RSVD2,
+ S2MPS15_REG_RSVD3,
+ S2MPS15_REG_RSVD4,
+ S2MPS15_REG_RSVD5,
+ S2MPS15_REG_RSVD6,
+ S2MPS15_REG_RSVD7,
+ S2MPS15_REG_RSVD8,
+ S2MPS15_REG_RSVD9,
+
+ S2MPS15_REG_WRSTBI_CTRL = 0x18,
+
+ S2MPS15_REG_BUCK1_CTRL = 0x19,
+ S2MPS15_REG_BUCK1_OUT,
+ S2MPS15_REG_BUCK2_CTRL = 0x1B,
+ S2MPS15_REG_BUCK2_OUT,
+ S2MPS15_REG_BUCK3_CTRL = 0x1D,
+ S2MPS15_REG_BUCK3_OUT,
+ S2MPS15_REG_BUCK4_CTRL = 0x1F,
+ S2MPS15_REG_BUCK4_OUT,
+ S2MPS15_REG_BUCK5_CTRL = 0x21,
+ S2MPS15_REG_BUCK5_OUT,
+ S2MPS15_REG_BUCK6_CTRL = 0x23,
+ S2MPS15_REG_BUCK6_OUT,
+ S2MPS15_REG_BUCK7_CTRL = 0x25,
+ S2MPS15_REG_BUCK7_OUT,
+ S2MPS15_REG_BUCK8_CTRL = 0x27,
+ S2MPS15_REG_BUCK8_OUT,
+ S2MPS15_REG_BUCK9_CTRL = 0x29,
+ S2MPS15_REG_BUCK9_OUT,
+ S2MPS15_REG_BUCK10_CTRL = 0x2B,
+ S2MPS15_REG_BUCK10_OUT,
+ S2MPS15_REG_BB1_CTRL = 0x2D,
+ S2MPS15_REG_BB1_OUT,
+ S2MPS15_REG_BUCK_RAMP,
+
+ S2MPS15_REG_LDO_DVS1 = 0x30,
+ S2MPS15_REG_LDO_DVS2,
+ S2MPS15_REG_LDO_DVS3,
+ S2MPS15_REG_LDO_DVS4,
+
+ S2MPS15_REG_LDO1_CTRL = 0x34,
+ S2MPS15_REG_LDO2_CTRL,
+ S2MPS15_REG_LDO3_CTRL,
+ S2MPS15_REG_LDO4_CTRL,
+ S2MPS15_REG_LDO5_CTRL,
+ S2MPS15_REG_LDO6_CTRL,
+ S2MPS15_REG_LDO7_CTRL,
+ S2MPS15_REG_LDO8_CTRL,
+ S2MPS15_REG_LDO9_CTRL,
+ S2MPS15_REG_LDO10_CTRL = 0x3D,
+ S2MPS15_REG_LDO11_CTRL,
+ S2MPS15_REG_LDO12_CTRL,
+ S2MPS15_REG_LDO13_CTRL,
+ S2MPS15_REG_LDO14_CTRL,
+ S2MPS15_REG_LDO15_CTRL,
+ S2MPS15_REG_LDO16_CTRL,
+ S2MPS15_REG_LDO17_CTRL,
+ S2MPS15_REG_LDO18_CTRL,
+ S2MPS15_REG_LDO19_CTRL,
+ S2MPS15_REG_LDO20_CTRL = 0x47,
+ S2MPS15_REG_LDO21_CTRL,
+ S2MPS15_REG_LDO22_CTRL,
+ S2MPS15_REG_LDO23_CTRL,
+ S2MPS15_REG_LDO24_CTRL,
+ S2MPS15_REG_LDO25_CTRL,
+ S2MPS15_REG_LDO26_CTRL,
+ S2MPS15_REG_LDO27_CTRL,
+
+ S2MPS15_REG_LDO_DCSH1 = 0x4F,
+ S2MPS15_REG_LDO_DCSH2,
+ S2MPS15_REG_LDO_DCSH3,
+ S2MPS15_REG_LDO_DCSH4,
+
+ S2MPS15_NUM_OF_REGS,
+};
+
+/* I2C device address for pmic s2mps15 */
+#define S2MPS15_I2C_ADDR 0x66
+
+/* LDO CTRL bit */
+#define OFF (0x0)
+#define ON (0x1)
+#define OUTPUT_OFF (~(3 << 6))
+#define OUTPUT_PWREN_ON (1 << 6)
+#define OUTPUT_LOWPWR_MODE (2 << 6)
+#define OUTPUT_NORMAL_MODE (3 << 6)
+
+/*
+ * RTC_BUF
+ */
+#define LOW_JITTER_EN (0x1 << 4)
+#define BT_32KHZ_EN (0x1 << 2)
+#define CP_32KHZ_EN (0x1 << 1)
+#define AP_32KHZ_EN (0x1 << 0)
+
+/*
+ * WRSTBI
+ */
+#define WRSTBI_EN (0x1 << 5)
+
+#define VDD_BASE_VOLT 50000
+#define VDD_VOLT_STEP 625
+#define MIN_VOLT 500
+#define MAX_RD_VAL 0xB0
+#define RD_BUCK_VOLT(x) (((x > MAX_RD_VAL) ? 0 : \
+ (((x - 0x10) * VDD_VOLT_STEP) + VDD_BASE_VOLT) / 100))
+#define WR_BUCK_VOLT(x) ((x < MIN_VOLT) ? 0x10 : \
+ ((((x) * 100) - VDD_BASE_VOLT) / VDD_VOLT_STEP + 0x10))
+
+#define PM_VDD_AP 900
+#define PM_VDD_MIF 1000
+#define PM_VDD_INT 1000
+#define PM_VDD_G3D 1000
+#define PM_VDD_DISP 1000
+
+#endif /* __S2MPS15_H_ */
More information about the coreboot-gerrit
mailing list