[coreboot-gerrit] Patch set updated for coreboot: Exynos7: Add initial PMU support
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Fri May 20 18:23:14 CEST 2016
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14905
-gerrit
commit e4721bf001c281059127df2bad0f80f22dab0d48
Author: Akshay Saraswat <akshay.s at samsung.com>
Date: Thu Aug 7 15:45:41 2014 +0530
Exynos7: Add initial PMU support
Introducing initial Power Management Unit support to setup CPU
power and state.
BUG=None
BRANCH=None
TEST=None
Change-Id: I1075c3148f817b4aa414fe0b69648390c729e5cc
Signed-off-by: Akshay Saraswat <akshay.s at samsung.com>
---
src/soc/samsung/exynos7/Makefile.inc | 3 ++
src/soc/samsung/exynos7/bootblock.c | 4 ++
src/soc/samsung/exynos7/include/soc/power.h | 83 +++++++++++++++++++++++++++++
src/soc/samsung/exynos7/power.c | 71 ++++++++++++++++++++++++
4 files changed, 161 insertions(+)
diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc
index b449e26..0fe90ad 100644
--- a/src/soc/samsung/exynos7/Makefile.inc
+++ b/src/soc/samsung/exynos7/Makefile.inc
@@ -19,11 +19,14 @@ INCLUDES += -Isrc/soc/samsung/exynos7/include/
# BOOTBLOCK : UART related and minimum required hardware init
bootblock-y += bootblock.c
+bootblock-y += power.c
# ROMSTAGE : Run primitive tests and remaining basic stuff
+romstage-y += power.c
# RAMSTAGE : Prepare and load payload
ramstage-y += cpu.c
+ramstage-y += power.c
$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
cp $< $@
diff --git a/src/soc/samsung/exynos7/bootblock.c b/src/soc/samsung/exynos7/bootblock.c
index 7336392..8af70de 100644
--- a/src/soc/samsung/exynos7/bootblock.c
+++ b/src/soc/samsung/exynos7/bootblock.c
@@ -19,9 +19,13 @@
#include <stdlib.h>
#include <soc/cpu.h>
+#include <soc/power.h>
void bootblock_cpu_init(void)
{
+ /* Set PS_HOLD and check reset status */
+ power_init();
+
/* SCR_EL3.NS|IRQ|FIQ|EA */
raw_write_scr_el3(raw_read_scr_el3() | 0xf);
diff --git a/src/soc/samsung/exynos7/include/soc/power.h b/src/soc/samsung/exynos7/include/soc/power.h
new file mode 100644
index 0000000..5240f68
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/power.h
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Register map for Exynos7 PMU */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_POWER_H_
+#define _CPU_SAMSUNG_EXYNOS7_POWER_H_
+
+#include <stddef.h>
+#include <soc/cpu.h>
+
+#define POWER_PS_HOLD_CONTROL_DATA_HIGH (1 << 8)
+#define POWER_ENABLE_HW_TRIP (1UL << 31)
+
+/* Power Management Unit register map */
+struct exynos_power {
+ /* Add registers as and when required */
+ unsigned int om_stat;
+ unsigned char reserved1[0x03fc];
+ unsigned int sw_reset;
+ unsigned char reserved2[0x0300];
+ unsigned int usb_dev_phy_ctrl;
+ unsigned char reserved5[0xf8];
+ unsigned int inform0;
+ unsigned int inform1;
+ unsigned int inform2;
+ unsigned int inform3;
+ unsigned char reserved6[0x0f0];
+ unsigned int spare0;
+ unsigned int spare1;
+ unsigned int spare2;
+ unsigned int spare3;
+ unsigned char reserved7[0x0f0];
+ unsigned int pmu_debug;
+ unsigned char reserved8[0x15fc];
+ struct {
+ unsigned int config;
+ unsigned int status;
+ unsigned char reserved[0x78];
+ } arm_core[4];
+ unsigned char reserved9[0xe04];
+ unsigned int padret_dram_status;
+ unsigned char reservedA[0xe0];
+ unsigned char reservedB[0x100];
+ unsigned int padret_dram_mif_opt;
+ unsigned char reservedC[0x120];
+ unsigned int ps_hold_ctrl;
+} __attribute__ ((__packed__));
+check_member(exynos_power, ps_hold_ctrl, 0x330c);
+
+/* Read the resume function and call it. */
+void power_exit_wakeup(void);
+
+/* Enable HW thermal trip */
+void power_enable_hw_thermal_trip(void);
+
+/* Initialize the pmic voltages to power up the system */
+void power_init(void);
+
+/* Read the reset status. */
+uint32_t power_read_reset_status(void);
+
+/* Perform a software reset */
+void power_reset(void);
+
+/**
+ * Power off the system; it should never return.
+ */
+void power_shutdown(void);
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_POWER_H_ */
diff --git a/src/soc/samsung/exynos7/power.c b/src/soc/samsung/exynos7/power.c
new file mode 100644
index 0000000..ce4fe35
--- /dev/null
+++ b/src/soc/samsung/exynos7/power.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Power setup code for EXYNOS7 */
+
+#include <arch/io.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include <soc/power.h>
+
+static struct exynos_power * const exynos_power = (void *)EXYNOS7_PMU_ALIVE_BASE;
+
+static void ps_hold_setup(void)
+{
+ /* Set PS-Hold high */
+ setbits_le32(&exynos_power->ps_hold_ctrl,
+ POWER_PS_HOLD_CONTROL_DATA_HIGH);
+}
+
+/* Enable HW thermal trip */
+void power_enable_hw_thermal_trip(void)
+{
+ setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
+}
+
+void power_exit_wakeup(void)
+{
+ uint64_t addr = (uint64_t)exynos_power->inform0;
+ typedef void (*resume_func)(void);
+
+ ((resume_func)addr)();
+}
+
+void power_init(void)
+{
+ ps_hold_setup();
+}
+
+uint32_t power_read_reset_status(void)
+{
+ return exynos_power->inform1;
+}
+
+void power_reset(void)
+{
+ /* Clear inform1 so there's no change we think we've got a wake reset */
+ exynos_power->inform1 = 0;
+
+ setbits_le32(&exynos_power->sw_reset, 1);
+}
+
+/* This function never returns */
+void power_shutdown(void)
+{
+ clrbits_le32(&exynos_power->ps_hold_ctrl,
+ POWER_PS_HOLD_CONTROL_DATA_HIGH);
+
+ hlt();
+}
More information about the coreboot-gerrit
mailing list