[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Use simpler macros for the northbridge PCI device
Alexandru Gagniuc (alexandrux.gagniuc@intel.com)
gerrit at coreboot.org
Thu May 19 19:27:35 CEST 2016
Alexandru Gagniuc (alexandrux.gagniuc at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14890
-gerrit
commit 3e9efdf56a84e151ade73ef3d4a866728791d20d
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date: Wed May 18 10:26:53 2016 -0700
soc/apollolake: Use simpler macros for the northbridge PCI device
The NB_DEV_ROOT macro, is almost unreadable, as it depends on other
stringified macros, and acts differently depending on the coreboot
stage. For ramstage, it also hides a function call.
Rewrite the macro in terms of more basic and readable macros. This
also means we can switch memmap.c to the __SIMPLE_DEVICE API, as the
functionality provided there is designed to be available in romstage,
so it does not need the full ramstage APIs.
Change-Id: I9b7071d67c8d58926e9b01fadaa239db1120448c
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
src/soc/intel/apollolake/chip.c | 2 +-
src/soc/intel/apollolake/include/soc/pci_devs.h | 12 +++---------
src/soc/intel/apollolake/memmap.c | 2 ++
3 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index f56e1f2..23dc892 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -100,7 +100,7 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
/* Load VBT before devicetree-specific config. */
silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
- struct device *dev = NB_DEV_ROOT;
+ struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
index ec550e8..d11b9a7 100644
--- a/src/soc/intel/apollolake/include/soc/pci_devs.h
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -17,26 +17,17 @@
#include <rules.h>
-#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0)
#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
-
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
#include <device/pci_def.h>
-#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot))
#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
#else
#include <arch/io.h>
-#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0)
#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
#endif
-/* North bridge devices */
-#define NB_DEV_SLOT_ROOT 0x00
-#define NB_DEVFN_ROOT _NB_DEVFN(ROOT)
-#define NB_DEV_ROOT _NB_DEV(ROOT)
-
/* LPSS UART */
#define LPSS_DEV_SLOT_UART 0x18
#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0)
@@ -48,6 +39,9 @@
#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
+#define NB_BUS 0
+#define NB_DEVFN PCI_DEVFN(0, 0)
+#define NB_DEV_ROOT PCI_DEV(NB_BUS, 0x0, 0)
#define P2SB_DEV PCI_DEV(0, 0xd, 0)
#define PMC_DEV PCI_DEV(0, 0xd, 1)
#define SPI_DEV PCI_DEV(0, 0xd, 2)
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index bf172cb..f2b483c 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -15,6 +15,8 @@
* GNU General Public License for more details.
*/
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <cbmem.h>
#include <device/pci.h>
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