[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: changes for image assembly

[Bora Guvendik (bora.guvendik@intel.com)]

Bora Guvendik (bora.guvendik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14897

-gerrit

commit c5c42ff24c51bc48457783b7e995b19ad65de53c
Author: Bora Guvendik <bora.guvendik at intel.com>
Date:   Wed May 18 14:56:27 2016 -0700

    soc/intel/apollolake: changes for image assembly
    
    Added changes to insert bootblock.
    
    BUG=
    BRANCH=none
    TEST=boots to chrome OS
    
    Change-Id: I0e92858486ecf4720b8bcdf64bae97d9476caabc
    Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
 src/mainboard/intel/amenia/Kconfig    | 28 ++++++++++++++++++++++++++--
 src/soc/intel/apollolake/Makefile.inc |  7 +++++++
 2 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig
index e83b151..2ed0e52 100644
--- a/src/mainboard/intel/amenia/Kconfig
+++ b/src/mainboard/intel/amenia/Kconfig
@@ -35,9 +35,22 @@ config FMAP_FILE
 	string
 	default "amenia"
 
-config PREBUILT_SPI_IMAGE
+config HAVE_IFD_BIN
+	default y
+
+config APOLLOLAKE_A0
+	bool
+	default y
+
+config IFD_BIN_PATH
+	string "Path and filename of the descriptor.bin file"
+	default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/reef.bin.orig.a0" if APOLLOLAKE_A0
+	default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/reef.bin.orig.b0" if !APOLLOLAKE_A0
+
+config FMDFILE
 	string
-	default "amenia.bin.orig.a0"
+	default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/reef.bin.orig.a0.fmd" if APOLLOLAKE_A0
+	default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/reef.bin.orig.b0.fmd" if !APOLLOLAKE_A0
 
 config IFD_BIOS_END
 	hex
@@ -47,6 +60,17 @@ config IFD_BIOS_START
 	hex
 	default 0x1000
 
+config FLASHMAP_OFFSET
+	hex
+	default 0x200000
+
+config IBBL_REGION
+	bool "Put bootblock.bin in seperate region"
+	default y
+	help
+	  Some SoC chips boot with the help of a CSE, and need their boot code
+	  to be placed in a different location than the end of ROM.
+
 config MAX_CPUS
 	int
 	default 8
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 240d3c2..d242ab5 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -60,4 +60,11 @@ postcar-y += tsc_freq.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
 
+build_complete::
+	$(CBFSTOOL) $(obj)/coreboot.rom write \
+		-r bootblock \
+		-f $(objcbfs)/bootblock.bin
+	$(CBFSTOOL) $(obj)/coreboot.rom write \
+		-r SIGN_CSE -u \
+		-f 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/signature2.bin
 endif