[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: enable RTC

[Jagadish Krishnamoorthy (jagadish.krishnamoorthy@intel.com)]

Jagadish Krishnamoorthy (jagadish.krishnamoorthy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14883

-gerrit

commit c6cf7aeb750f7b3c3b1cee387c4474cc8a67d24a
Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Date:   Tue May 17 18:06:49 2016 -0700

    soc/intel/apollolake: enable RTC
    
    BUG=none
    TEST=Boot to OS and verfiy if rtc0 device is created
    under /sys/class/rtc/
    
    Change-Id: Idec569255859816fda467bb42a215c00f7c0e16e
    Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
---
 src/soc/intel/apollolake/include/soc/pm.h |  1 +
 src/soc/intel/apollolake/lpc.c            | 46 +++++++++++++++++++++++++++++++
 src/soc/intel/apollolake/pmutil.c         |  6 ++++
 3 files changed, 53 insertions(+)

diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index fe7a423..7aa5ebf 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -143,5 +143,6 @@ void disable_pm1_control(uint32_t mask);
 void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
+uint32_t get_pmcon1_reg(void);
 
 #endif
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 48dfb1f..a5f7f9a 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -15,13 +15,18 @@
  * GNU General Public License for more details.
  */
 
+#include <cbmem.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
 #include <soc/acpi.h>
 #include <soc/lpc.h>
 #include <soc/pci_ids.h>
+#include <soc/pm.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <vendorcode/google/chromeos/vbnv_layout.h>
 
 #include "chip.h"
 
@@ -43,6 +48,44 @@
  * opens up IO and memory windows as needed.
  */
 
+/*
+ * Preserve Vboot NV data when clearing CMOS as it will
+ * have been re-initialized already by Vboot firmware init.
+ */
+static void rtc_init_preserve(int rtc_fail)
+{
+	uint8_t vbnv[VBNV_BLOCK_SIZE];
+
+	read_vbnv(vbnv);
+	if (rtc_fail)
+		read_vbnv(vbnv);
+
+	cmos_init(rtc_fail);
+
+	if (rtc_fail)
+		save_vbnv(vbnv);
+}
+
+static void rtc_init(void)
+{
+	uint32_t gen_pmcon1;
+	int rtc_fail;
+	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+
+	if (ps != NULL)
+		gen_pmcon1 = ps->gen_pmcon1;
+	else
+		gen_pmcon1 = get_pmcon1_reg();
+
+	rtc_fail = !!(gen_pmcon1 & RPS);
+	/* Ensure the date is set including century byte. */
+	cmos_check_update_date();
+	if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS))
+		rtc_init_preserve(rtc_fail);
+	else
+		cmos_init(rtc_fail);
+}
+
 static void lpc_init(struct device *dev)
 {
 	uint8_t scnt;
@@ -61,6 +104,9 @@ static void lpc_init(struct device *dev)
 	else if (cfg->serirq_mode == SERIRQ_CONTINUOUS)
 		scnt |= SCNT_EN | SCNT_MODE;
 	pci_write_config8(dev, REG_SERIRQ_CTL, scnt);
+
+	/* Initialize RTC */
+	rtc_init();
 }
 
 static void soc_lpc_add_io_resources(device_t dev)
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 16c8a04..9b19b5e 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -265,6 +265,12 @@ uint32_t clear_gpe_status(void)
 	return print_gpe_sts(reset_gpe_status());
 }
 
+uint32_t get_pmcon1_reg(void)
+{
+	uintptr_t pmc_bar0 = read_pmc_mmio_bar();
+	return read32((void *)(pmc_bar0 + GEN_PMCON1));
+}
+
 void clear_pmc_status(void)
 {
 	uint32_t prsts;