[coreboot-gerrit] New patch to review for coreboot: soc/apollolake: Add ish_enable in soc_intel_apollolake_config
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Wed May 18 20:52:57 CEST 2016
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14894
-gerrit
commit 7eef81a75aba8723bdc2bba1a4f6ad65c5652854
Author: Hannah Williams <hannah.williams at intel.com>
Date: Mon Mar 28 14:45:59 2016 -0700
soc/apollolake: Add ish_enable in soc_intel_apollolake_config
Also initialize IshEnable in Silicon Init UPD with the value from
devicetree.cb
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
Change-Id: I8f57a7353471cc3efa21c7011cdd0b369d25275d
---
src/soc/intel/apollolake/chip.c | 2 ++
src/soc/intel/apollolake/chip.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 6e0a90f..7a2399d 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -106,6 +106,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
/* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
silconfig->PmcBase = PMC_BAR0 + 0x1000;
silconfig->P2sbBase = P2SB_BAR;
+
+ silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
}
struct chip_operations soc_intel_apollolake_ops = {
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index d74084e..3d9f5bd 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -42,6 +42,9 @@ struct soc_intel_apollolake_config {
/* Configure serial IRQ (SERIRQ) line. */
enum serirq_mode serirq_mode;
+
+ /* Integrated Sensor Hub */
+ uint8_t integrated_sensor_hub_enable;
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
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