[coreboot-gerrit] Patch merged into coreboot/master: rk3399: add GPIO register definitions for SDMMC0

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit a9cd4a2f117f03abb4e4433b040c2225242fd35f
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Thu May 12 16:40:37 2016 +0800

    rk3399: add GPIO register definitions for SDMMC0
    
    The code needs to be able to set drive strength for the pins used for
    SDMMC0 interface. This patch adds the definitions for the two
    registers, as per page 378 of the RK3399 TRM Part 1.
    
    Instead of calculation of the reserved range size just use known
    offsets of the registers included in the structure.
    
    BRANCH=none
    BUG=chrome-os-partner:53257
    TEST=with the upcoming driver change it is possible to boot chrome OS
         on Gru from various micro SD cards which were failing before.
    
    Change-Id: I63bf37432ec7f3bdf7e9c6a79d51c31de122dae9
    Signed-off-by: Martin Roth <martinroth at google.com>
    Original-Commit-Id: c6d6dc5e5e6cc81c173603d4eb21ae803a47815d
    Original-Change-Id: Ibe7584e77b446435ab1264dcf8fc8bfe0c50438e
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/344490
    Original-Reviewed-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: https://review.coreboot.org/14852
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>


See https://review.coreboot.org/14852 for details.

-gerrit