[coreboot-gerrit] Patch set updated for coreboot: AGESA boards: Split dispatcher to romstage and ramstage
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed May 18 15:46:19 CEST 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14417
-gerrit
commit 2321fa943f44d3cdd25a72c2e22c784e183f8d02
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Apr 19 15:18:02 2016 +0300
AGESA boards: Split dispatcher to romstage and ramstage
The way dispatcher table is set up prevents linker from
optimizing unused code away, we currently have raminit in ramstage.
Optimize this manually by configuring AGESA_ENTRY booleans for
romstage and ramstage separately. This will remove references in
FuncParamsInfo and DispatchTable -arrays.
All boards now include multi-core dispatcher, it has minimal footprint:
AGESA_ENTRY_LATE_RUN_AP_TASK
ACPI S3 support depends on HAVE_ACPI_RESUME being enabled:
AGESA_ENTRY_INIT_RESUME
AGESA_ENTRY_INIT_LATE_RESTORE
AGESA_ENTRY_INIT_S3SAVE
Disabled for all boards as it was not used:
AGESA_ENTRY_INIT_GENERAL_SERVICES
Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/amd/dinar/buildOpts.c | 17 --
src/mainboard/amd/inagua/buildOpts.c | 15 --
src/mainboard/amd/olivehill/buildOpts.c | 12 -
src/mainboard/amd/parmer/buildOpts.c | 12 -
src/mainboard/amd/persimmon/buildOpts.c | 15 --
src/mainboard/amd/south_station/buildOpts.c | 15 --
src/mainboard/amd/thatcher/buildOpts.c | 12 -
src/mainboard/amd/torpedo/buildOpts.c | 16 --
src/mainboard/amd/union_station/buildOpts.c | 15 --
src/mainboard/asrock/e350m1/buildOpts.c | 16 --
src/mainboard/asrock/imb-a180/buildOpts.c | 12 -
src/mainboard/asus/f2a85-m/buildOpts.c | 12 -
src/mainboard/asus/f2a85-m_le/buildOpts.c | 12 -
src/mainboard/bap/ode_e20XX/buildOpts.c | 13 --
src/mainboard/biostar/am1ml/buildOpts.c | 12 -
src/mainboard/gizmosphere/gizmo/buildOpts.c | 15 --
src/mainboard/gizmosphere/gizmo2/buildOpts.c | 13 --
src/mainboard/hp/abm/buildOpts.c | 12 -
src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 12 -
src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 15 --
src/mainboard/lenovo/g505s/buildOpts.c | 12 -
src/mainboard/lippert/frontrunner-af/buildOpts.c | 15 --
src/mainboard/lippert/toucan-af/buildOpts.c | 15 --
src/mainboard/pcengines/apu1/buildOpts.c | 15 --
src/mainboard/supermicro/h8qgi/buildOpts.c | 12 -
src/mainboard/supermicro/h8scm/buildOpts.c | 12 -
src/mainboard/tyan/s8226/buildOpts.c | 12 -
src/vendorcode/amd/agesa/common/Makefile.inc | 3 +
src/vendorcode/amd/agesa/common/agesa-entry-cfg.h | 86 +++++++
src/vendorcode/amd/agesa/common/agesa-entry.c | 177 +++++++++++++++
.../amd/agesa/f10/Include/OptionDmiInstall.h | 2 -
.../amd/agesa/f10/Include/OptionHtAssistInstall.h | 2 -
.../amd/agesa/f12/Include/OptionDmiInstall.h | 2 -
.../agesa/f12/Include/OptionL3FeaturesInstall.h | 2 -
.../amd/agesa/f12/Include/OptionPstateInstall.h | 2 +-
.../amd/agesa/f12/Include/PlatformInstall.h | 246 +-------------------
.../amd/agesa/f14/Include/OptionDmiInstall.h | 2 -
.../amd/agesa/f14/Include/OptionHtAssistInstall.h | 2 -
.../amd/agesa/f14/Include/PlatformInstall.h | 247 +-------------------
.../amd/agesa/f15/Include/OptionDmiInstall.h | 2 -
.../agesa/f15/Include/OptionL3FeaturesInstall.h | 2 -
.../amd/agesa/f15/Include/PlatformInstall.h | 247 +-------------------
.../amd/agesa/f15tn/Include/OptionDmiInstall.h | 2 -
.../agesa/f15tn/Include/OptionL3FeaturesInstall.h | 2 -
.../amd/agesa/f15tn/Include/PlatformInstall.h | 247 +-------------------
.../amd/agesa/f16kb/Include/OptionDmiInstall.h | 2 -
.../agesa/f16kb/Include/OptionL3FeaturesInstall.h | 2 -
.../f16kb/Include/OptionPrefetchModeInstall.h | 2 -
.../amd/agesa/f16kb/Include/PlatformInstall.h | 251 +--------------------
49 files changed, 277 insertions(+), 1621 deletions(-)
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
index 6ac5ed8..efed4b7 100644
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -26,7 +26,6 @@
*/
#include <stdlib.h>
#include "AGESA.h"
-#include "CommonReturns.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
@@ -153,24 +152,9 @@
#define BLDCFG_PSTATE_HPC_MODE FALSE
#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap
-/*
- * Agesa entry points used in this implementation.
- */
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE//FALSE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
-#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
/*****************************************************************************
@@ -395,7 +379,6 @@ CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] =
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
-#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index b4651b6..ffaf79a 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -101,20 +101,6 @@
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -218,7 +204,6 @@
* needed by the system.
*/
#include "AGESA.h"
-#include "CommonReturns.h"
/* The fixed MTRR values to be set after memory initialization. */
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c
index 153d856..106e1c1 100644
--- a/src/mainboard/amd/olivehill/buildOpts.c
+++ b/src/mainboard/amd/olivehill/buildOpts.c
@@ -171,17 +171,6 @@
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
* Customized OEM build configurations for FCH component
*/
@@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
-#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index e7ee47d..11d36bc 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -172,17 +172,6 @@
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
* Customized OEM build configurations for FCH component
*/
@@ -252,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
-#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index 1ded047..fe4e779 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -101,20 +101,6 @@
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -218,7 +204,6 @@
* needed by the system.
*/
#include "AGESA.h"
-#include "CommonReturns.h"
/* The fixed MTRR values to be set after memory initialization. */
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 7f07ea1..2f696ef 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -101,20 +101,6 @@
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -218,7 +204,6 @@
* needed by the system.
*/
#include "AGESA.h"
-#include "CommonReturns.h"
/* The fixed MTRR values to be set after memory initialization. */
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index a26f697..45569df 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -172,17 +172,6 @@
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
* Customized OEM build configurations for FCH component
*/
@@ -252,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
-#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index 9abc651..40f1f97 100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -27,7 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
-#include "CommonReturns.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
@@ -83,20 +82,6 @@
//For revision C single-link processors
#define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*****************************************************************************
* Define the RELEASE VERSION string
@@ -230,7 +215,6 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
-#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 7f07ea1..2f696ef 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -101,20 +101,6 @@
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -218,7 +204,6 @@
* needed by the system.
*/
#include "AGESA.h"
-#include "CommonReturns.h"
/* The fixed MTRR values to be set after memory initialization. */
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index 2fba932..d030423 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -27,7 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
-#include "CommonReturns.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
@@ -103,20 +102,6 @@
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
/*
* Agesa configuration values selection.
@@ -246,7 +231,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
-#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c
index a21b55d..4fd8347 100644
--- a/src/mainboard/asrock/imb-a180/buildOpts.c
+++ b/src/mainboard/asrock/imb-a180/buildOpts.c
@@ -171,17 +171,6 @@
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
* Customized OEM build configurations for FCH component
*/
@@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
-#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index 17ce5d2..5413b7c 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -31,7 +31,6 @@
/* Include the files that instantiate the configuration definitions. */
#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
-#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
@@ -187,17 +186,6 @@
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
* Customized OEM build configurations for FCH component
*/
diff --git a/src/mainboard/asus/f2a85-m_le/buildOpts.c b/src/mainboard/asus/f2a85-m_le/buildOpts.c
index 8233482..f702396 100644
--- a/src/mainboard/asus/f2a85-m_le/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m_le/buildOpts.c
@@ -31,7 +31,6 @@
/* Include the files that instantiate the configuration definitions. */
#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
-#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
@@ -187,17 +186,6 @@
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
* Customized OEM build configurations for FCH component
*/
diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c
index 80cb79f..eb67d95 100644
--- a/src/mainboard/bap/ode_e20XX/buildOpts.c
+++ b/src/mainboard/bap/ode_e20XX/buildOpts.c
@@ -27,7 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
-//#include "CommonReturns.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
@@ -172,17 +171,6 @@
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
* Customized OEM build configurations for FCH component
*/
@@ -253,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
-#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c
index 4f910df..9514ab4 100644
--- a/src/mainboard/biostar/am1ml/buildOpts.c
+++ b/src/mainboard/biostar/am1ml/buildOpts.c
@@ -171,17 +171,6 @@
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
* Customized OEM build configurations for FCH component
*/
@@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
-#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c
index c838bab..f26559f 100644
--- a/src/mainboard/gizmosphere/gizmo/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c
@@ -103,20 +103,6 @@
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -220,7 +206,6 @@
* needed by the system.
*/
#include "AGESA.h"
-#include "CommonReturns.h"
/* The fixed MTRR values to be set after memory initialization. */
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c
index 80cb79f..eb67d95 100644
--- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c
@@ -27,7 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
-//#include "CommonReturns.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
@@ -172,17 +171,6 @@
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
* Customized OEM build configurations for FCH component
*/
@@ -253,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
-#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c
index c24dd4d..2c623f2 100644
--- a/src/mainboard/hp/abm/buildOpts.c
+++ b/src/mainboard/hp/abm/buildOpts.c
@@ -176,17 +176,6 @@
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
* Customized OEM build configurations for FCH component
*/
@@ -256,7 +245,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
-#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index f4b61ab..7300771 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -33,7 +33,6 @@
/* Include the files that instantiate the configuration definitions. */
#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
-#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
@@ -188,17 +187,6 @@
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
* Customized OEM build configurations for FCH component
*/
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index 05ea681..24337ef 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -31,7 +31,6 @@
/* Include the files that instantiate the configuration definitions. */
#include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h>
-#include <vendorcode/amd/agesa/f14/Include/CommonReturns.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
@@ -115,20 +114,6 @@
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-/*
- * AGESA entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index d633d07..a1abfc8 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -33,7 +33,6 @@
/* Include the files that instantiate the configuration definitions. */
#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
-#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
@@ -188,17 +187,6 @@
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
* Customized OEM build configurations for FCH component
*/
diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c
index c17394a..345bff8 100644
--- a/src/mainboard/lippert/frontrunner-af/buildOpts.c
+++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c
@@ -102,20 +102,6 @@
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -219,7 +205,6 @@
* needed by the system.
*/
#include "AGESA.h"
-#include "CommonReturns.h"
/* The fixed MTRR values to be set after memory initialization. */
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c
index c17394a..345bff8 100644
--- a/src/mainboard/lippert/toucan-af/buildOpts.c
+++ b/src/mainboard/lippert/toucan-af/buildOpts.c
@@ -102,20 +102,6 @@
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -219,7 +205,6 @@
* needed by the system.
*/
#include "AGESA.h"
-#include "CommonReturns.h"
/* The fixed MTRR values to be set after memory initialization. */
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c
index edfdd30..f7d99c0 100644
--- a/src/mainboard/pcengines/apu1/buildOpts.c
+++ b/src/mainboard/pcengines/apu1/buildOpts.c
@@ -101,20 +101,6 @@
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-/*
- * Agesa entry points used in this implementation.
- */
-#define AGESA_ENTRY_INIT_RESET TRUE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -218,7 +204,6 @@
* needed by the system.
*/
#include "AGESA.h"
-#include "CommonReturns.h"
/* The fixed MTRR values to be set after memory initialization. */
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
index 14ca2f7..13a0d89 100644
--- a/src/mainboard/supermicro/h8qgi/buildOpts.c
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
@@ -16,7 +16,6 @@
#include <stdlib.h>
#include "AGESA.h"
-#include "CommonReturns.h"
#include "AdvancedApi.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
@@ -425,17 +424,6 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE//FALSE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
#if CONFIG_CPU_AMD_AGESA_FAMILY15
diff --git a/src/mainboard/supermicro/h8scm/buildOpts.c b/src/mainboard/supermicro/h8scm/buildOpts.c
index 2716689..6d30ad1 100644
--- a/src/mainboard/supermicro/h8scm/buildOpts.c
+++ b/src/mainboard/supermicro/h8scm/buildOpts.c
@@ -16,7 +16,6 @@
#include <stdlib.h>
#include "AGESA.h"
-#include "CommonReturns.h"
#include "AdvancedApi.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
@@ -338,17 +337,6 @@ CONST AP_MTRR_SETTINGS ROMDATA h8scm_ap_mtrr_list[] =
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE//FALSE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
#include "SanMarinoInstall.h"
diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c
index b462210..86134b5 100644
--- a/src/mainboard/tyan/s8226/buildOpts.c
+++ b/src/mainboard/tyan/s8226/buildOpts.c
@@ -16,7 +16,6 @@
#include <stdlib.h>
#include "AGESA.h"
-#include "CommonReturns.h"
#include "AdvancedApi.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
@@ -425,17 +424,6 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
-#define AGESA_ENTRY_INIT_RESET TRUE//FALSE
-#define AGESA_ENTRY_INIT_RECOVERY FALSE
-#define AGESA_ENTRY_INIT_EARLY TRUE
-#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_MID TRUE
-#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE TRUE
-#define AGESA_ENTRY_INIT_RESUME TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
#if CONFIG_CPU_AMD_AGESA_FAMILY15
diff --git a/src/vendorcode/amd/agesa/common/Makefile.inc b/src/vendorcode/amd/agesa/common/Makefile.inc
index 9853546..efc42ee 100644
--- a/src/vendorcode/amd/agesa/common/Makefile.inc
+++ b/src/vendorcode/amd/agesa/common/Makefile.inc
@@ -27,6 +27,9 @@
#
#*****************************************************************************
+romstage-y += agesa-entry.c
+ramstage-y += agesa-entry.c
+
libagesa-y += amdlib.c
# Do not optimise performance-critical low-level IO for size with -Os,
diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
new file mode 100644
index 0000000..e882f2e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
@@ -0,0 +1,86 @@
+#ifndef AGESA_ENTRY_CFG_H
+#define AGESA_ENTRY_CFG_H
+
+
+#if defined(__PRE_RAM__)
+
+#define AGESA_ENTRY_INIT_RESET TRUE
+#define AGESA_ENTRY_INIT_EARLY TRUE
+#define AGESA_ENTRY_INIT_POST TRUE
+
+/* Not implemented in coreboot romstage. */
+#define AGESA_ENTRY_INIT_RECOVERY FALSE
+
+#define AGESA_ENTRY_INIT_RESUME IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#define AGESA_ENTRY_INIT_LATE_RESTORE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+
+/* Move to ramstage? */
+#define AGESA_ENTRY_INIT_ENV TRUE
+
+#else
+
+#define AGESA_ENTRY_INIT_MID TRUE
+#define AGESA_ENTRY_INIT_LATE TRUE
+#define AGESA_ENTRY_INIT_S3SAVE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+
+#endif
+
+/* Not required. */
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
+
+/* Required for any multi-core. */
+#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+
+
+/* Defaults below. */
+
+/* Process user desired AGESA entry points */
+#ifndef AGESA_ENTRY_INIT_RESET
+ #define AGESA_ENTRY_INIT_RESET FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RECOVERY
+ #define AGESA_ENTRY_INIT_RECOVERY FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_EARLY
+ #define AGESA_ENTRY_INIT_EARLY FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_POST
+ #define AGESA_ENTRY_INIT_POST FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_ENV
+ #define AGESA_ENTRY_INIT_ENV FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_MID
+ #define AGESA_ENTRY_INIT_MID FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE
+ #define AGESA_ENTRY_INIT_LATE FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_S3SAVE
+ #define AGESA_ENTRY_INIT_S3SAVE FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RESUME
+ #define AGESA_ENTRY_INIT_RESUME FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
+ #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
+ #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
+#endif
+
+#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK
+ #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+#endif
+
+#endif /* AGESA_ENTRY_CFG_H */
diff --git a/src/vendorcode/amd/agesa/common/agesa-entry.c b/src/vendorcode/amd/agesa/common/agesa-entry.c
new file mode 100644
index 0000000..e722fc1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/common/agesa-entry.c
@@ -0,0 +1,177 @@
+#include <Porting.h>
+#include <AMD.h>
+#include <AGESA.h>
+
+#include "CommonReturns.h"
+
+#include <heapManager.h>
+#include <CreateStruct.h>
+
+#include <Options.h>
+
+#include <agesa-entry-cfg.h>
+
+CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
+{
+ #if AGESA_ENTRY_INIT_RESET == TRUE
+ { AMD_INIT_RESET,
+ sizeof (AMD_RESET_PARAMS),
+ (PF_AGESA_FUNCTION) AmdInitResetConstructor,
+ (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+ AMD_INIT_RESET_HANDLE
+ },
+ #endif
+
+ #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+ { AMD_INIT_RECOVERY,
+ sizeof (AMD_RECOVERY_PARAMS),
+ (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
+ (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+ AMD_INIT_POST_HANDLE
+ },
+ #endif
+
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ { AMD_INIT_EARLY,
+ sizeof (AMD_EARLY_PARAMS),
+ (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
+ (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+ AMD_INIT_EARLY_HANDLE
+ },
+ #endif
+
+ #if AGESA_ENTRY_INIT_ENV == TRUE
+ { AMD_INIT_ENV,
+ sizeof (AMD_ENV_PARAMS),
+ (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
+ (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+ AMD_INIT_ENV_HANDLE
+ },
+ #endif
+
+ #if AGESA_ENTRY_INIT_LATE == TRUE
+ { AMD_INIT_LATE,
+ sizeof (AMD_LATE_PARAMS),
+ (PF_AGESA_FUNCTION) AmdInitLateInitializer,
+ (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
+ AMD_INIT_LATE_HANDLE
+ },
+ #endif
+
+ #if AGESA_ENTRY_INIT_MID == TRUE
+ { AMD_INIT_MID,
+ sizeof (AMD_MID_PARAMS),
+ (PF_AGESA_FUNCTION) AmdInitMidInitializer,
+ (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+ AMD_INIT_MID_HANDLE
+ },
+ #endif
+
+ #if AGESA_ENTRY_INIT_POST == TRUE
+ { AMD_INIT_POST,
+ sizeof (AMD_POST_PARAMS),
+ (PF_AGESA_FUNCTION) AmdInitPostInitializer,
+ (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
+ AMD_INIT_POST_HANDLE
+ },
+ #endif
+
+ #if AGESA_ENTRY_INIT_RESUME == TRUE
+ { AMD_INIT_RESUME,
+ sizeof (AMD_RESUME_PARAMS),
+ (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
+ (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
+ AMD_INIT_RESUME_HANDLE
+ },
+ #endif
+
+ #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+ { AMD_S3LATE_RESTORE,
+ sizeof (AMD_S3LATE_PARAMS),
+ (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
+ (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+ AMD_S3_LATE_RESTORE_HANDLE
+ },
+ #endif
+
+ #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+ { AMD_S3_SAVE,
+ sizeof (AMD_S3SAVE_PARAMS),
+ (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
+ (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
+ AMD_S3_SAVE_HANDLE
+ },
+ #endif
+
+ #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+ { AMD_LATE_RUN_AP_TASK,
+ sizeof (AP_EXE_PARAMS),
+ (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
+ (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+ AMD_LATE_RUN_AP_TASK_HANDLE
+ },
+ #endif
+ { 0, 0, NULL }
+};
+
+CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
+
+CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
+{
+ { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
+ { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
+
+ #if AGESA_ENTRY_INIT_RESET == TRUE
+ { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
+ #endif
+
+ #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+ { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
+ #endif
+
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
+ #endif
+
+ #if AGESA_ENTRY_INIT_POST == TRUE
+ { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
+ #endif
+
+ #if AGESA_ENTRY_INIT_ENV == TRUE
+ { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
+ #endif
+
+ #if AGESA_ENTRY_INIT_MID == TRUE
+ { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
+ #endif
+
+ #if AGESA_ENTRY_INIT_LATE == TRUE
+ { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
+ #endif
+
+ #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+ { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
+ #endif
+
+ #if AGESA_ENTRY_INIT_RESUME == TRUE
+ { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
+ #endif
+
+ #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+ { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
+ #endif
+
+ #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+ { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
+ { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
+ { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
+ { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
+ { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
+ { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
+ #endif
+
+ #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+ { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
+ #endif
+ { 0, NULL }
+};
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h
index 2ad7792..232d407 100644
--- a/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h
@@ -60,8 +60,6 @@
#define USER_DMI_OPTION &GetDmiInfoMain
#define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
#ifdef OPTION_FAMILY10H
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h
index c084924..a7149f0 100644
--- a/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h
@@ -79,8 +79,6 @@
&HtAssistFamilyServiceArray[0]
};
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#undef HT_ASSIST_AP_DISABLE_CACHE
#define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
#undef HT_ASSIST_AP_ENABLE_CACHE
diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h
index 410d3cb..ead4fce 100644
--- a/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h
@@ -63,8 +63,6 @@
// This additional check keeps AP launch routines from being unnecessarily included
// in single socket systems.
#if OPTION_MULTISOCKET == TRUE
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
#else
#define CPU_DMI_AP_GET_TYPE4_TYPE7
diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h
index f3ef633..7f3ac07 100644
--- a/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h
@@ -82,8 +82,6 @@
#endif
#endif
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#undef L3_FEAT_AP_DISABLE_CACHE
#define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
#undef L3_FEAT_AP_ENABLE_CACHE
diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h
index d52adfb..7d6433d 100644
--- a/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h
@@ -129,7 +129,7 @@
#if AGESA_ENTRY_INIT_LATE == TRUE
#define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables
#else
- OPTION_ACPI_FEATURE CreateAcpiTablesStub;
+// OPTION_ACPI_FEATURE CreateAcpiTablesStub;
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
diff --git a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h
index dce81a2..171adb5 100644
--- a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h
@@ -52,30 +52,6 @@
*
****************************************************************************/
-/* Available options for image builds.
- *
- * As part of the image build for each image, define the options below to select the
- * AGESA entry points included in that image. Turn these on in your option c file, not
- * here.
- */
-// #define AGESA_ENTRY_INIT_RESET TRUE
-// #define AGESA_ENTRY_INIT_RECOVERY TRUE
-// #define AGESA_ENTRY_INIT_EARLY TRUE
-// #define AGESA_ENTRY_INIT_POST TRUE
-// #define AGESA_ENTRY_INIT_ENV TRUE
-// #define AGESA_ENTRY_INIT_MID TRUE
-// #define AGESA_ENTRY_INIT_LATE TRUE
-// #define AGESA_ENTRY_INIT_S3SAVE TRUE
-// #define AGESA_ENTRY_INIT_RESUME TRUE
-// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
-
-/* Defaults for private/internal build control settings */
-/* Available options for image builds.
- *
- * As part of the image build for each image, define the options below to select the
- * AGESA entry points included in that image.
- */
VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
//ModuleHeaderSignature
@@ -91,61 +67,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
NULL
};
-/* Process user desired AGESA entry points */
-#ifndef AGESA_ENTRY_INIT_RESET
- #define AGESA_ENTRY_INIT_RESET FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_RECOVERY
- #define AGESA_ENTRY_INIT_RECOVERY FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_EARLY
- #define AGESA_ENTRY_INIT_EARLY FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_POST
- #define AGESA_ENTRY_INIT_POST FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_ENV
- #define AGESA_ENTRY_INIT_ENV FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_MID
- #define AGESA_ENTRY_INIT_MID FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_LATE
- #define AGESA_ENTRY_INIT_LATE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_S3SAVE
- #define AGESA_ENTRY_INIT_S3SAVE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_RESUME
- #define AGESA_ENTRY_INIT_RESUME FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
- #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
- #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
-#endif
-
-/* Default the late AP entry point to off. It can be enabled
- by any family that may need the late AP functionality, or
- by any feature code that may need it. The IBVs no longer
- have control over this entry point. */
-#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
-#endif
-#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE
-
-
/* Process solution defined socket / family installations
*
@@ -2293,6 +2214,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
* Include the structure definitions for the defaults table structures
*
****************************************************************************/
+#include <CommonReturns.h>
+#include <agesa-entry-cfg.h>
#include "Options.h"
#include "OptionCpuFamiliesInstall.h"
#include "OptionsHt.h"
@@ -2508,171 +2431,6 @@ BUILD_OPT_CFG UserOptions = {
0, //reserved...
};
-CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
-{
- #if AGESA_ENTRY_INIT_RESET == TRUE
- { AMD_INIT_RESET,
- sizeof (AMD_RESET_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitResetConstructor,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_RESET_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_RECOVERY == TRUE
- { AMD_INIT_RECOVERY,
- sizeof (AMD_RECOVERY_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_POST_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- { AMD_INIT_EARLY,
- sizeof (AMD_EARLY_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_EARLY_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_ENV == TRUE
- { AMD_INIT_ENV,
- sizeof (AMD_ENV_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_ENV_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE == TRUE
- { AMD_INIT_LATE,
- sizeof (AMD_LATE_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitLateInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
- AMD_INIT_LATE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_MID == TRUE
- { AMD_INIT_MID,
- sizeof (AMD_MID_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitMidInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_MID_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_POST == TRUE
- { AMD_INIT_POST,
- sizeof (AMD_POST_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitPostInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
- AMD_INIT_POST_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_RESUME == TRUE
- { AMD_INIT_RESUME,
- sizeof (AMD_RESUME_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
- AMD_INIT_RESUME_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- { AMD_S3LATE_RESTORE,
- sizeof (AMD_S3LATE_PARAMS),
- (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_S3_LATE_RESTORE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_S3SAVE == TRUE
- { AMD_S3_SAVE,
- sizeof (AMD_S3SAVE_PARAMS),
- (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
- (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
- AMD_S3_SAVE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
- { AMD_LATE_RUN_AP_TASK,
- sizeof (AP_EXE_PARAMS),
- (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_LATE_RUN_AP_TASK_HANDLE
- },
- #endif
- { 0, 0, NULL }
-};
-
-CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
-
-CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
-{
- { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
- { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
-
- #if AGESA_ENTRY_INIT_RESET == TRUE
- { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
- #endif
-
- #if AGESA_ENTRY_INIT_RECOVERY == TRUE
- { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
- #endif
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
- #endif
-
- #if AGESA_ENTRY_INIT_POST == TRUE
- { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
- #endif
-
- #if AGESA_ENTRY_INIT_ENV == TRUE
- { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
- #endif
-
- #if AGESA_ENTRY_INIT_MID == TRUE
- { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE == TRUE
- { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
- #endif
-
- #if AGESA_ENTRY_INIT_S3SAVE == TRUE
- { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
- #endif
-
- #if AGESA_ENTRY_INIT_RESUME == TRUE
- { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
- #endif
-
- #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
- { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
- { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
- { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
- { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
- { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
- { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
- #endif
-
- #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
- { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
- #endif
- { 0, NULL }
-};
-
CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
{
IDS_LATE_RUN_AP_TASK
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h
index 31111e3..eb4bc91 100644
--- a/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h
@@ -66,8 +66,6 @@
// This additional check keeps AP launch routines from being unnecessarily included
// in single socket systems.
#if OPTION_MULTISOCKET == TRUE
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
#else
#define CPU_DMI_AP_GET_TYPE4_TYPE7
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h
index d98300f..175482b 100644
--- a/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h
@@ -97,8 +97,6 @@
&HtAssistFamilyServiceArray[0]
};
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#undef HT_ASSIST_AP_DISABLE_CACHE
#define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
#undef HT_ASSIST_AP_ENABLE_CACHE
diff --git a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h
index 6e54aa9..8092ad2 100644
--- a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h
@@ -51,31 +51,6 @@
*
****************************************************************************/
-/* Available options for image builds.
- *
- * As part of the image build for each image, define the options below to select the
- * AGESA entry points included in that image. Turn these on in your option c file, not
- * here.
- */
-// #define AGESA_ENTRY_INIT_RESET TRUE
-// #define AGESA_ENTRY_INIT_RECOVERY TRUE
-// #define AGESA_ENTRY_INIT_EARLY TRUE
-// #define AGESA_ENTRY_INIT_POST TRUE
-// #define AGESA_ENTRY_INIT_ENV TRUE
-// #define AGESA_ENTRY_INIT_MID TRUE
-// #define AGESA_ENTRY_INIT_LATE TRUE
-// #define AGESA_ENTRY_INIT_S3SAVE TRUE
-// #define AGESA_ENTRY_INIT_RESUME TRUE
-// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
-
-/* Defaults for private/internal build control settings */
-/* Available options for image builds.
- *
- * As part of the image build for each image, define the options below to select the
- * AGESA entry points included in that image.
- */
-
VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
//ModuleHeaderSignature
// Remove 'DOM$' as temp solution before update BinUtil.exe ,
@@ -90,62 +65,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
NULL
};
-/* Process user desired AGESA entry points */
-#ifndef AGESA_ENTRY_INIT_RESET
- #define AGESA_ENTRY_INIT_RESET FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_RECOVERY
- #define AGESA_ENTRY_INIT_RECOVERY FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_EARLY
- #define AGESA_ENTRY_INIT_EARLY FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_POST
- #define AGESA_ENTRY_INIT_POST FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_ENV
- #define AGESA_ENTRY_INIT_ENV FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_MID
- #define AGESA_ENTRY_INIT_MID FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_LATE
- #define AGESA_ENTRY_INIT_LATE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_S3SAVE
- #define AGESA_ENTRY_INIT_S3SAVE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_RESUME
- #define AGESA_ENTRY_INIT_RESUME FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
- #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
- #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
-#endif
-
-/* Default the late AP entry point to off. It can be enabled
- by any family that may need the late AP functionality, or
- by any feature code that may need it. The IBVs no longer
- have control over this entry point. */
-#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
-#endif
-#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE
-
-
-
/* Process solution defined socket / family installations
*
* As part of the release package for each image, define the options below to select the
@@ -2180,6 +2099,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
* Include the structure definitions for the defaults table structures
*
****************************************************************************/
+#include <CommonReturns.h>
+#include <agesa-entry-cfg.h>
#include "Options.h"
#include "OptionCpuFamiliesInstall.h"
#include "OptionsHt.h"
@@ -2353,170 +2274,6 @@ BUILD_OPT_CFG UserOptions = {
0, //reserved...
};
-CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
-{
- #if AGESA_ENTRY_INIT_RESET == TRUE
- { AMD_INIT_RESET,
- sizeof (AMD_RESET_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitResetConstructor,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_RESET_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_RECOVERY == TRUE
- { AMD_INIT_RECOVERY,
- sizeof (AMD_RECOVERY_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_POST_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- { AMD_INIT_EARLY,
- sizeof (AMD_EARLY_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_EARLY_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_ENV == TRUE
- { AMD_INIT_ENV,
- sizeof (AMD_ENV_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_ENV_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE == TRUE
- { AMD_INIT_LATE,
- sizeof (AMD_LATE_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitLateInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
- AMD_INIT_LATE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_MID == TRUE
- { AMD_INIT_MID,
- sizeof (AMD_MID_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitMidInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_MID_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_POST == TRUE
- { AMD_INIT_POST,
- sizeof (AMD_POST_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitPostInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
- AMD_INIT_POST_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_RESUME == TRUE
- { AMD_INIT_RESUME,
- sizeof (AMD_RESUME_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
- AMD_INIT_RESUME_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- { AMD_S3LATE_RESTORE,
- sizeof (AMD_S3LATE_PARAMS),
- (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_S3_LATE_RESTORE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_S3SAVE == TRUE
- { AMD_S3_SAVE,
- sizeof (AMD_S3SAVE_PARAMS),
- (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
- (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
- AMD_S3_SAVE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
- { AMD_LATE_RUN_AP_TASK,
- sizeof (AP_EXE_PARAMS),
- (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_LATE_RUN_AP_TASK_HANDLE
- },
- #endif
- { 0, 0, NULL }
-};
-
-CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
-
-CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
-{
- { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
- { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
-
- #if AGESA_ENTRY_INIT_RESET == TRUE
- { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
- #endif
-
- #if AGESA_ENTRY_INIT_RECOVERY == TRUE
- { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
- #endif
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
- #endif
-
- #if AGESA_ENTRY_INIT_POST == TRUE
- { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
- #endif
-
- #if AGESA_ENTRY_INIT_ENV == TRUE
- { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
- #endif
-
- #if AGESA_ENTRY_INIT_MID == TRUE
- { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE == TRUE
- { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
- #endif
-
- #if AGESA_ENTRY_INIT_S3SAVE == TRUE
- { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
- #endif
-
- #if AGESA_ENTRY_INIT_RESUME == TRUE
- { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
- #endif
-
- #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
- { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
- { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
- { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
- { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
- { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
- { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
- #endif
-
- #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
- { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
- #endif
- { 0, NULL }
-};
CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
{
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h
index a6d48b3..b09a58f 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h
@@ -64,8 +64,6 @@
// This additional check keeps AP launch routines from being unnecessarily included
// in single socket systems.
#if OPTION_MULTISOCKET == TRUE
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
#else
#define CPU_DMI_AP_GET_TYPE4_TYPE7
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h
index 5804f1d..4a73c40 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h
@@ -94,8 +94,6 @@
#endif
#endif
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#undef L3_FEAT_AP_DISABLE_CACHE
#define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
#undef L3_FEAT_AP_ENABLE_CACHE
diff --git a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h
index db331c9..7d96fef 100644
--- a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h
@@ -49,31 +49,6 @@
*
****************************************************************************/
-/* Available options for image builds.
- *
- * As part of the image build for each image, define the options below to select the
- * AGESA entry points included in that image. Turn these on in your option c file, not
- * here.
- */
-// #define AGESA_ENTRY_INIT_RESET TRUE
-// #define AGESA_ENTRY_INIT_RECOVERY TRUE
-// #define AGESA_ENTRY_INIT_EARLY TRUE
-// #define AGESA_ENTRY_INIT_POST TRUE
-// #define AGESA_ENTRY_INIT_ENV TRUE
-// #define AGESA_ENTRY_INIT_MID TRUE
-// #define AGESA_ENTRY_INIT_LATE TRUE
-// #define AGESA_ENTRY_INIT_S3SAVE TRUE
-// #define AGESA_ENTRY_INIT_RESUME TRUE
-// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
-
-/* Defaults for private/internal build control settings */
-/* Available options for image builds.
- *
- * As part of the image build for each image, define the options below to select the
- * AGESA entry points included in that image.
- */
-
VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
//ModuleHeaderSignature
// Remove 'DOM$' as temp solution before update BinUtil.exe ,
@@ -88,61 +63,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
NULL
};
-/* Process user desired AGESA entry points */
-#ifndef AGESA_ENTRY_INIT_RESET
- #define AGESA_ENTRY_INIT_RESET FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_RECOVERY
- #define AGESA_ENTRY_INIT_RECOVERY FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_EARLY
- #define AGESA_ENTRY_INIT_EARLY FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_POST
- #define AGESA_ENTRY_INIT_POST FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_ENV
- #define AGESA_ENTRY_INIT_ENV FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_MID
- #define AGESA_ENTRY_INIT_MID FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_LATE
- #define AGESA_ENTRY_INIT_LATE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_S3SAVE
- #define AGESA_ENTRY_INIT_S3SAVE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_RESUME
- #define AGESA_ENTRY_INIT_RESUME FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
- #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
- #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
-#endif
-
-/* Default the late AP entry point to off. It can be enabled
- by any family that may need the late AP functionality, or
- by any feature code that may need it. The IBVs no longer
- have control over this entry point. */
-#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
-#endif
-#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE
-
-
/* Process solution defined socket / family installations
*
@@ -2279,6 +2199,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
* Include the structure definitions for the defaults table structures
*
****************************************************************************/
+#include <CommonReturns.h>
+#include <agesa-entry-cfg.h>
#include "Options.h"
#include "OptionCpuFamiliesInstall.h"
#include "OptionsHt.h"
@@ -2528,171 +2450,6 @@ BUILD_OPT_CFG UserOptions = {
0, //reserved...
};
-CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
-{
- #if AGESA_ENTRY_INIT_RESET == TRUE
- { AMD_INIT_RESET,
- sizeof (AMD_RESET_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitResetConstructor,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_RESET_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_RECOVERY == TRUE
- { AMD_INIT_RECOVERY,
- sizeof (AMD_RECOVERY_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_POST_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- { AMD_INIT_EARLY,
- sizeof (AMD_EARLY_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_EARLY_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_ENV == TRUE
- { AMD_INIT_ENV,
- sizeof (AMD_ENV_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_ENV_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE == TRUE
- { AMD_INIT_LATE,
- sizeof (AMD_LATE_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitLateInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
- AMD_INIT_LATE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_MID == TRUE
- { AMD_INIT_MID,
- sizeof (AMD_MID_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitMidInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_MID_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_POST == TRUE
- { AMD_INIT_POST,
- sizeof (AMD_POST_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitPostInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
- AMD_INIT_POST_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_RESUME == TRUE
- { AMD_INIT_RESUME,
- sizeof (AMD_RESUME_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
- AMD_INIT_RESUME_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- { AMD_S3LATE_RESTORE,
- sizeof (AMD_S3LATE_PARAMS),
- (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_S3_LATE_RESTORE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_S3SAVE == TRUE
- { AMD_S3_SAVE,
- sizeof (AMD_S3SAVE_PARAMS),
- (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
- (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
- AMD_S3_SAVE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
- { AMD_LATE_RUN_AP_TASK,
- sizeof (AP_EXE_PARAMS),
- (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_LATE_RUN_AP_TASK_HANDLE
- },
- #endif
- { 0, 0, NULL, NULL, 0 }
-};
-
-CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
-
-CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
-{
- { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
- { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
-
- #if AGESA_ENTRY_INIT_RESET == TRUE
- { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
- #endif
-
- #if AGESA_ENTRY_INIT_RECOVERY == TRUE
- { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
- #endif
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
- #endif
-
- #if AGESA_ENTRY_INIT_POST == TRUE
- { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
- #endif
-
- #if AGESA_ENTRY_INIT_ENV == TRUE
- { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
- #endif
-
- #if AGESA_ENTRY_INIT_MID == TRUE
- { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE == TRUE
- { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
- #endif
-
- #if AGESA_ENTRY_INIT_S3SAVE == TRUE
- { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
- #endif
-
- #if AGESA_ENTRY_INIT_RESUME == TRUE
- { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
- #endif
-
- #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
- { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
- { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
- { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
- { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
- { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
- { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
- #endif
-
- #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
- { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
- #endif
- { 0, NULL }
-};
-
CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
{
IDS_LATE_RUN_AP_TASK
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h
index fb1b54d..541cee9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h
@@ -63,8 +63,6 @@
// This additional check keeps AP launch routines from being unnecessarily included
// in single socket systems.
#if OPTION_MULTISOCKET == TRUE
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
#else
#define CPU_DMI_AP_GET_TYPE4_TYPE7
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h
index 5d188e2..203b9e2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h
@@ -82,8 +82,6 @@
#endif
#endif
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#undef L3_FEAT_AP_DISABLE_CACHE
#define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
#undef L3_FEAT_AP_ENABLE_CACHE
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h
index 7fcfd7d..d91cec8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h
@@ -48,31 +48,6 @@
*
****************************************************************************/
-/* Available options for image builds.
- *
- * As part of the image build for each image, define the options below to select the
- * AGESA entry points included in that image. Turn these on in your option c file, not
- * here.
- */
-// #define AGESA_ENTRY_INIT_RESET TRUE
-// #define AGESA_ENTRY_INIT_RECOVERY TRUE
-// #define AGESA_ENTRY_INIT_EARLY TRUE
-// #define AGESA_ENTRY_INIT_POST TRUE
-// #define AGESA_ENTRY_INIT_ENV TRUE
-// #define AGESA_ENTRY_INIT_MID TRUE
-// #define AGESA_ENTRY_INIT_LATE TRUE
-// #define AGESA_ENTRY_INIT_S3SAVE TRUE
-// #define AGESA_ENTRY_INIT_RESUME TRUE
-// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
-
-/* Defaults for private/internal build control settings */
-/* Available options for image builds.
- *
- * As part of the image build for each image, define the options below to select the
- * AGESA entry points included in that image.
- */
-
VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
//ModuleHeaderSignature
// Remove 'DOM$' as temp solution before update BinUtil.exe ,
@@ -87,61 +62,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
NULL
};
-/* Process user desired AGESA entry points */
-#ifndef AGESA_ENTRY_INIT_RESET
- #define AGESA_ENTRY_INIT_RESET FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_RECOVERY
- #define AGESA_ENTRY_INIT_RECOVERY FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_EARLY
- #define AGESA_ENTRY_INIT_EARLY FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_POST
- #define AGESA_ENTRY_INIT_POST FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_ENV
- #define AGESA_ENTRY_INIT_ENV FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_MID
- #define AGESA_ENTRY_INIT_MID FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_LATE
- #define AGESA_ENTRY_INIT_LATE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_S3SAVE
- #define AGESA_ENTRY_INIT_S3SAVE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_RESUME
- #define AGESA_ENTRY_INIT_RESUME FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
- #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
- #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
-#endif
-
-/* Default the late AP entry point to off. It can be enabled
- by any family that may need the late AP functionality, or
- by any feature code that may need it. The IBVs no longer
- have control over this entry point. */
-#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
-#endif
-#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE
-
-
/* Process solution defined socket / family installations
*
@@ -2648,6 +2568,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
* Include the structure definitions for the defaults table structures
*
****************************************************************************/
+#include <CommonReturns.h>
+#include <agesa-entry-cfg.h>
#include "Options.h"
#include "OptionCpuFamiliesInstall.h"
#include "OptionsHt.h"
@@ -2912,171 +2834,6 @@ BUILD_OPT_CFG UserOptions = {
0, //reserved...
};
-CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
-{
- #if AGESA_ENTRY_INIT_RESET == TRUE
- { AMD_INIT_RESET,
- sizeof (AMD_RESET_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitResetConstructor,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_RESET_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_RECOVERY == TRUE
- { AMD_INIT_RECOVERY,
- sizeof (AMD_RECOVERY_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_POST_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- { AMD_INIT_EARLY,
- sizeof (AMD_EARLY_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_EARLY_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_ENV == TRUE
- { AMD_INIT_ENV,
- sizeof (AMD_ENV_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_ENV_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE == TRUE
- { AMD_INIT_LATE,
- sizeof (AMD_LATE_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitLateInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
- AMD_INIT_LATE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_MID == TRUE
- { AMD_INIT_MID,
- sizeof (AMD_MID_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitMidInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_MID_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_POST == TRUE
- { AMD_INIT_POST,
- sizeof (AMD_POST_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitPostInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
- AMD_INIT_POST_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_RESUME == TRUE
- { AMD_INIT_RESUME,
- sizeof (AMD_RESUME_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
- AMD_INIT_RESUME_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- { AMD_S3LATE_RESTORE,
- sizeof (AMD_S3LATE_PARAMS),
- (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_S3_LATE_RESTORE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_S3SAVE == TRUE
- { AMD_S3_SAVE,
- sizeof (AMD_S3SAVE_PARAMS),
- (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
- (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
- AMD_S3_SAVE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
- { AMD_LATE_RUN_AP_TASK,
- sizeof (AP_EXE_PARAMS),
- (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_LATE_RUN_AP_TASK_HANDLE
- },
- #endif
- { 0, 0, NULL, NULL, 0 }
-};
-
-CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
-
-CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
-{
- { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
- { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
-
- #if AGESA_ENTRY_INIT_RESET == TRUE
- { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
- #endif
-
- #if AGESA_ENTRY_INIT_RECOVERY == TRUE
- { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
- #endif
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
- #endif
-
- #if AGESA_ENTRY_INIT_POST == TRUE
- { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
- #endif
-
- #if AGESA_ENTRY_INIT_ENV == TRUE
- { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
- #endif
-
- #if AGESA_ENTRY_INIT_MID == TRUE
- { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE == TRUE
- { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
- #endif
-
- #if AGESA_ENTRY_INIT_S3SAVE == TRUE
- { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
- #endif
-
- #if AGESA_ENTRY_INIT_RESUME == TRUE
- { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
- #endif
-
- #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
- { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
- { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
- { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
- { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
- { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
- { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
- #endif
-
- #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
- { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
- #endif
- { 0, NULL }
-};
-
CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
{
IDS_LATE_RUN_AP_TASK
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h
index ce8ef06..e0b09b3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h
@@ -75,8 +75,6 @@ OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
// This additional check keeps AP launch routines from being unnecessarily included
// in single socket systems.
#if OPTION_MULTISOCKET == TRUE
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#undef CPU_DMI_AP_GET_TYPE4_TYPE7
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h
index 8d34603..3323fea 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h
@@ -57,8 +57,6 @@
#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE || OPTION_NBR_CACHE == TRUE)
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#undef L3_FEAT_AP_DISABLE_CACHE
#define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
#undef L3_FEAT_AP_ENABLE_CACHE
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h
index aa510aa..711b1a3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h
@@ -57,8 +57,6 @@
#if OPTION_PREFETCH_MODE == TRUE
#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#undef CPU_PREFETCH_MODE_AP_TASK
#define CPU_PREFETCH_MODE_AP_TASK {AP_LATE_TASK_CPU_PREFETCH_MODE, (IMAGE_ENTRY) CpuPrefetchModeApTask},
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
index e989537..a313bbb 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
@@ -48,31 +48,6 @@
*
****************************************************************************/
-/* Available options for image builds.
- *
- * As part of the image build for each image, define the options below to select the
- * AGESA entry points included in that image. Turn these on in your option c file, not
- * here.
- */
-// #define AGESA_ENTRY_INIT_RESET TRUE
-// #define AGESA_ENTRY_INIT_RECOVERY TRUE
-// #define AGESA_ENTRY_INIT_EARLY TRUE
-// #define AGESA_ENTRY_INIT_POST TRUE
-// #define AGESA_ENTRY_INIT_ENV TRUE
-// #define AGESA_ENTRY_INIT_MID TRUE
-// #define AGESA_ENTRY_INIT_LATE TRUE
-// #define AGESA_ENTRY_INIT_S3SAVE TRUE
-// #define AGESA_ENTRY_INIT_RESUME TRUE
-// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
-
-/* Defaults for private/internal build control settings */
-/* Available options for image builds.
- *
- * As part of the image build for each image, define the options below to select the
- * AGESA entry points included in that image.
- */
-
VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
//ModuleHeaderSignature
// Remove 'DOM$' as temp solution before update BinUtil.exe ,
@@ -87,62 +62,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
NULL
};
-/* Process user desired AGESA entry points */
-#ifndef AGESA_ENTRY_INIT_RESET
- #define AGESA_ENTRY_INIT_RESET FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_RECOVERY
- #define AGESA_ENTRY_INIT_RECOVERY FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_EARLY
- #define AGESA_ENTRY_INIT_EARLY FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_POST
- #define AGESA_ENTRY_INIT_POST FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_ENV
- #define AGESA_ENTRY_INIT_ENV FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_MID
- #define AGESA_ENTRY_INIT_MID FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_LATE
- #define AGESA_ENTRY_INIT_LATE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_S3SAVE
- #define AGESA_ENTRY_INIT_S3SAVE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_RESUME
- #define AGESA_ENTRY_INIT_RESUME FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
- #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
- #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
-#endif
-
-/* Default the late AP entry point to off. It can be enabled
- by any family that may need the late AP functionality, or
- by any feature code that may need it. The IBVs no longer
- have control over this entry point. */
-#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
-#endif
-#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE
-
-
-
/* Process solution defined socket / family installations
*
* As part of the release package for each image, define the options below to select the
@@ -1727,6 +1646,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
* Include the structure definitions for the defaults table structures
*
****************************************************************************/
+#include <CommonReturns.h>
+#include <agesa-entry-cfg.h>
#include "Options.h"
#include "OptionCpuFamiliesInstall.h"
#include "OptionsHt.h"
@@ -2007,174 +1928,6 @@ BUILD_OPT_CFG UserOptions = {
0, //reserved...
};
-CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
-{
- #if AGESA_ENTRY_INIT_RESET == TRUE
- { AMD_INIT_RESET,
- sizeof (AMD_RESET_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitResetConstructor,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_RESET_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_RECOVERY == TRUE
- { AMD_INIT_RECOVERY,
- sizeof (AMD_RECOVERY_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_POST_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- { AMD_INIT_EARLY,
- sizeof (AMD_EARLY_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_EARLY_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_ENV == TRUE
- { AMD_INIT_ENV,
- sizeof (AMD_ENV_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_ENV_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE == TRUE
- { AMD_INIT_LATE,
- sizeof (AMD_LATE_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitLateInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
- AMD_INIT_LATE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_MID == TRUE
- { AMD_INIT_MID,
- sizeof (AMD_MID_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitMidInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_MID_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_POST == TRUE
- { AMD_INIT_POST,
- sizeof (AMD_POST_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitPostInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
- AMD_INIT_POST_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_RESUME == TRUE
- { AMD_INIT_RESUME,
- sizeof (AMD_RESUME_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
- AMD_INIT_RESUME_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- { AMD_S3LATE_RESTORE,
- sizeof (AMD_S3LATE_PARAMS),
- (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_S3_LATE_RESTORE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_S3SAVE == TRUE
- { AMD_S3_SAVE,
- sizeof (AMD_S3SAVE_PARAMS),
- (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
- (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
- AMD_S3_SAVE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
- { AMD_LATE_RUN_AP_TASK,
- sizeof (AP_EXE_PARAMS),
- (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_LATE_RUN_AP_TASK_HANDLE
- },
- #endif
- { 0, 0, NULL, NULL, 0 }
-};
-
-CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
-
-CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
-{
- { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
- { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
-
- #if AGESA_ENTRY_INIT_RESET == TRUE
- { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
- #endif
-
- #if AGESA_ENTRY_INIT_RECOVERY == TRUE
- { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
- #endif
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
- #endif
-
- #if AGESA_ENTRY_INIT_POST == TRUE
- { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
- #if OPTION_DATA_EYE == TRUE
- { AMD_GET_2D_DATA_EYE, (IMAGE_ENTRY)AmdGet2DDataEye },
- #endif
- #endif
-
- #if AGESA_ENTRY_INIT_ENV == TRUE
- { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
- #endif
-
- #if AGESA_ENTRY_INIT_MID == TRUE
- { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE == TRUE
- { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
- #endif
-
- #if AGESA_ENTRY_INIT_S3SAVE == TRUE
- { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
- #endif
-
- #if AGESA_ENTRY_INIT_RESUME == TRUE
- { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
- #endif
-
- #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
- { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
- { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
- { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
- { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
- { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
- { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
- #endif
-
- #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
- { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
- #endif
- { 0, NULL }
-};
-
CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
{
IDS_LATE_RUN_AP_TASK
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