[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: enable RTC

[Jagadish Krishnamoorthy (jagadish.krishnamoorthy@intel.com)]

Jagadish Krishnamoorthy (jagadish.krishnamoorthy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14883

-gerrit

commit 0366f86345ad15a773d66614112128806055e084
Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Date:   Tue May 17 18:06:49 2016 -0700

    soc/intel/apollolake: enable RTC
    
    BUG=none
    TEST=Boot to OS and verfiy if rtc0 device is created
    under /sys/class/rtc/
    
    Change-Id: Idec569255859816fda467bb42a215c00f7c0e16e
    Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
---
 src/soc/intel/apollolake/include/soc/pm.h |  1 +
 src/soc/intel/apollolake/lpc.c            | 25 +++++++++++++++++++++++++
 src/soc/intel/apollolake/pmutil.c         |  6 ++++++
 3 files changed, 32 insertions(+)

diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index fe7a423..7aa5ebf 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -143,5 +143,6 @@ void disable_pm1_control(uint32_t mask);
 void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
+uint32_t get_pmcon1_reg(void);
 
 #endif
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 48dfb1f..f328175 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -15,13 +15,16 @@
  * GNU General Public License for more details.
  */
 
+#include <cbmem.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
 #include <soc/acpi.h>
 #include <soc/lpc.h>
 #include <soc/pci_ids.h>
+#include <soc/pm.h>
 
 #include "chip.h"
 
@@ -43,6 +46,25 @@
  * opens up IO and memory windows as needed.
  */
 
+static void rtc_init(void)
+{
+	uint32_t gen_pmcon1;
+	int rtc_fail;
+	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+
+	if (ps != NULL) {
+		gen_pmcon1 = ps->gen_pmcon1;
+	} else {
+		gen_pmcon1 = get_pmcon1_reg();
+	}
+	rtc_fail = !!(gen_pmcon1 & RPS);
+	if (rtc_fail) {
+		printk(BIOS_ERR, "RTC failure, weak or missing battery\n");
+	}
+
+	cmos_init(rtc_fail);
+}
+
 static void lpc_init(struct device *dev)
 {
 	uint8_t scnt;
@@ -61,6 +83,9 @@ static void lpc_init(struct device *dev)
 	else if (cfg->serirq_mode == SERIRQ_CONTINUOUS)
 		scnt |= SCNT_EN | SCNT_MODE;
 	pci_write_config8(dev, REG_SERIRQ_CTL, scnt);
+
+	/* Initialize RTC */
+	rtc_init();
 }
 
 static void soc_lpc_add_io_resources(device_t dev)
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 16c8a04..9b19b5e 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -265,6 +265,12 @@ uint32_t clear_gpe_status(void)
 	return print_gpe_sts(reset_gpe_status());
 }
 
+uint32_t get_pmcon1_reg(void)
+{
+	uintptr_t pmc_bar0 = read_pmc_mmio_bar();
+	return read32((void *)(pmc_bar0 + GEN_PMCON1));
+}
+
 void clear_pmc_status(void)
 {
 	uint32_t prsts;