[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp2_0: Add recipes for FSP blobs
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Tue May 17 06:30:37 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14802
-gerrit
commit 68964dce60da88b6560397fc3cc5b5a62b03173b
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Fri Apr 15 21:33:18 2016 -0700
drivers/intel/fsp2_0: Add recipes for FSP blobs
Add Kconfig options and Makefile recipes that include FSP
blobs in CBFS.
Change-Id: I678a3541e51e5fb3515f7038484bc27890a16f1d
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/drivers/intel/fsp2_0/Kconfig | 28 ++++++++++++++++++++++++++++
src/drivers/intel/fsp2_0/Makefile.inc | 10 ++++++++++
src/soc/intel/apollolake/Kconfig | 6 ++++++
src/soc/intel/apollolake/Makefile.inc | 3 +++
4 files changed, 47 insertions(+)
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 19e04f7..6cfacad 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -3,4 +3,32 @@ config PLATFORM_USES_FSP2_0
help
Include FSP 2.0 wrappers and functionality
+if PLATFORM_USES_FSP2_0
+config ADD_FSP_BINARIES
+ bool "Add Intel FSP 2.0 binaries to CBFS"
+ help
+ Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not
+ use the FSP-T binary and it is not added.
+
+config FSP_S_CBFS
+ string "Name of FSP-S in CBFS"
+ default "fsps.bin"
+
+config FSP_M_CBFS
+ string "Name of FSP-M in CBFS"
+ default "fspm.bin"
+
+config FSP_M_FILE
+ string "Intel FSP-M (memory init) binary path and filename"
+ depends on ADD_FSP_BINARIES
+ help
+ The path and filename of the Intel FSP-M binary for this platform.
+
+config FSP_S_FILE
+ string "Intel FSP-S (silicon init) binary path and filename"
+ depends on ADD_FSP_BINARIES
+ help
+ The path and filename of the Intel FSP-S binary for this platform.
+
+endif
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index 3e94f2f..ff82390 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -25,4 +25,14 @@ ramstage-y += util.c
CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
+# Add FSP blobs into cbfs. SoC code may supply additional options with
+# -options, e.g --xip or -b
+cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS)
+$(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE))
+$(CONFIG_FSP_M_CBFS)-type := fsp
+
+cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_S_CBFS)
+$(CONFIG_FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE))
+$(CONFIG_FSP_S_CBFS)-type := fsp
+
endif
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 41a96c9..4f4128d 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -118,6 +118,12 @@ config ROMSTAGE_ADDR
help
The base address (in CAR) where romstage should be linked
+config FSP_M_ADDR
+ hex
+ default 0xfef60000
+ help
+ The address FSP-M will be relocated to during build time
+
config CACHE_MRC_SETTINGS
bool
default y
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 240d3c2..63732b1 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -60,4 +60,7 @@ postcar-y += tsc_freq.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
+# Since FSP-M runs in CAR we need to relocate it to a specific address
+$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR)
+
endif
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