[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp2_0: Add recipes for FSP blobs

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14802

-gerrit

commit 73c97d6779dea6386b814c4db3e2d8e353e56c80
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Fri Apr 15 21:33:18 2016 -0700

    drivers/intel/fsp2_0: Add recipes for FSP blobs
    
    Add Kconfig options and Makefile recipes that include FSP
    blobs in CBFS.
    
    Change-Id: I678a3541e51e5fb3515f7038484bc27890a16f1d
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/drivers/intel/fsp2_0/Kconfig      | 28 ++++++++++++++++++++++++++++
 src/drivers/intel/fsp2_0/Makefile.inc |  9 +++++++++
 src/soc/intel/apollolake/Kconfig      |  6 ++++++
 3 files changed, 43 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 19e04f7..6cfacad 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -3,4 +3,32 @@ config PLATFORM_USES_FSP2_0
 	help
 	  Include FSP 2.0 wrappers and functionality
 
+if PLATFORM_USES_FSP2_0
 
+config ADD_FSP_BINARIES
+	bool "Add Intel FSP 2.0 binaries to CBFS"
+	help
+	  Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not
+	  use the FSP-T binary and it is not added.
+
+config FSP_S_CBFS
+	string "Name of FSP-S in CBFS"
+	default "fsps.bin"
+
+config FSP_M_CBFS
+	string "Name of FSP-M in CBFS"
+	default "fspm.bin"
+
+config FSP_M_FILE
+	string "Intel FSP-M (memory init) binary path and filename"
+	depends on ADD_FSP_BINARIES
+	help
+	  The path and filename of the Intel FSP-M binary for this platform.
+
+config FSP_S_FILE
+	string "Intel FSP-S (silicon init) binary path and filename"
+	depends on ADD_FSP_BINARIES
+	help
+	  The path and filename of the Intel FSP-S binary for this platform.
+
+endif
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index 3e94f2f..041565d 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -25,4 +25,13 @@ ramstage-y += util.c
 
 CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
 
+cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS)
+$(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE))
+$(CONFIG_FSP_M_CBFS)-type := fsp
+$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR)
+
+cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_S_CBFS)
+$(CONFIG_FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE))
+$(CONFIG_FSP_S_CBFS)-type := fsp
+
 endif
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 41a96c9..4f4128d 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -118,6 +118,12 @@ config ROMSTAGE_ADDR
 	help
 	  The base address (in CAR) where romstage should be linked
 
+config FSP_M_ADDR
+	hex
+	default 0xfef60000
+	help
+	  The address FSP-M will be relocated to during build time
+
 config CACHE_MRC_SETTINGS
 	bool
 	default y