[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Enable ACPI PM1 timer emulation

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14821

-gerrit

commit dbfa201ee0c2bc17ab68a115a13d51587a694253
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Tue Mar 29 14:19:53 2016 -0700

    soc/intel/apollolake: Enable ACPI PM1 timer emulation
    
    This change supposedly enables emulation for ACPI PM1 timer.
    Unfortuntely no documentation is available at this point of
    time. Current FSP MemoryInit uses the timer for memory
    training and will fail if the timer is not functioning.
    
    Change-Id: I7a441f5f1673e6430697615ae7251da948e77548
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/bootblock/bootblock.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 833f531..43f61a5 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include <lib.h>
 #include <soc/bootblock.h>
+#include <soc/iomap.h>
 #include <soc/cpu.h>
 #include <soc/gpio.h>
 #include <soc/northbridge.h>
@@ -36,6 +37,17 @@ static void tpm_enable(void)
 	gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
 }
 
+static void enable_pm_timer(void)
+{
+	/* ACPI PM timer emulation */
+	msr_t msr;
+	/* Presumably this is divider configuration to get 3.579545MHz freq */
+	msr.hi = 0x2FBA2E25;
+	/* Presumably this sets up PM1 timer IO port */
+	msr.lo = (1<<16) | (ACPI_PMIO_BASE + R_ACPI_PM1_TMR);
+	wrmsr(0x121, msr);
+}
+
 void asmlinkage bootblock_c_entry(void)
 {
 	device_t dev = NB_DEV_ROOT;
@@ -80,5 +92,7 @@ void bootblock_soc_early_init(void)
 	if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI))
 		tpm_enable();
 
+	enable_pm_timer();
+
 	cache_bios_region();
 }