[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Work around FSP-M CAR layout
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Mon May 16 18:49:40 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14804
-gerrit
commit a66757cb6e6d575351455ede316a2b3153c97ca5
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Sat Apr 23 14:28:21 2016 -0700
soc/intel/apollolake: Work around FSP-M CAR layout
As of now FSP-M can not be relocated and it can not be instructed
to use a specific resource for temporary memory. As result coreboot
is forced to use CAR layout dictated by default FSP-M configuration.
Change CAR size to 1MiB, link romstage at such CAR address so it
doesn't overlap with FSP-M's default heap/stack.
Change-Id: I56f78f043099dc835e294dbc081d7506bfad280d
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/soc/intel/apollolake/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 7bbc6da..5d936ae 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -73,7 +73,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM"
- default 0x80000
+ default 0x100000
help
The size of the cache-as-ram region required during bootblock
and/or romstage.
@@ -116,7 +116,7 @@ config X86_TOP4G_BOOTMEDIA_MAP
config ROMSTAGE_ADDR
hex
- default 0xfef2e000
+ default 0xfef3e000
help
The base address (in CAR) where romstage should be linked
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