[coreboot-gerrit] New patch to review for coreboot: soc/intel/quark: Add GPIO register access
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Mon May 16 17:12:46 CEST 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14825
-gerrit
commit e00a05c0bb7cfeb2702805b64e530cacfe858cd2
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sun May 15 13:32:24 2016 -0700
soc/intel/quark: Add GPIO register access
Add register access routines for the GPIO and legacy GPIO controllers.
TEST=Build and run on Galileo Gen2
Change-Id: I0c023428f4784de9e025279480554b8ed134afca
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/soc/intel/quark/include/soc/pci_devs.h | 20 ++++++--
src/soc/intel/quark/include/soc/reg_access.h | 48 +++++++++++++++++++
src/soc/intel/quark/reg_access.c | 70 ++++++++++++++++++++++++++++
3 files changed, 133 insertions(+), 5 deletions(-)
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
index a912c4c..9d4e116 100644
--- a/src/soc/intel/quark/include/soc/pci_devs.h
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -26,16 +26,26 @@
#define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN)
/* Device IDs */
+#define I2CGPIO_DEVID 0x0934
#define HSUART_DEVID 0x0936
#define EHCI_DEVID 0x0939
/* IO Fabric 1 */
-#define SIO1_DEV 0x14
-# define HSUART1_DEV SIO1_DEV
-# define HSUART1_FUNC 5
+#define SIO1_DEV 0x14
+#define HSUART1_DEV SIO1_DEV
+#define HSUART1_FUNC 5
+
+/* IO Fabric 2 */
+#define SIO2_DEV 0x15
+#define I2CGPIO_DEV SIO2_DEV
+#define I2CGPIO_FUNC 2
+#define I2CGPIO_DEV_FUNC PCI_DEVFN(I2CGPIO_DEV, I2CGPIO_FUNC)
+#define I2CGPIO_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, I2CGPIO_DEV, I2CGPIO_FUNC)
/* Platform Controller Unit */
-# define LPC_DEV_FUNC PCI_DEVFN(PCI_DEVICE_NUMBER_QNC_LPC, \
- PCI_FUNCTION_NUMBER_QNC_LPC)
+#define LPC_DEV PCI_DEVICE_NUMBER_QNC_LPC
+#define LPC_FUNC PCI_FUNCTION_NUMBER_QNC_LPC
+#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC)
+#define LPC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, LPC_DEV, LPC_FUNC)
#endif /* _QUARK_PCI_DEVS_H_ */
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h
index c6b786a..c1b0df0 100644
--- a/src/soc/intel/quark/include/soc/reg_access.h
+++ b/src/soc/intel/quark/include/soc/reg_access.h
@@ -20,6 +20,7 @@
#include <fsp/util.h>
#include <reg_script.h>
#include <soc/IntelQNCConfig.h>
+#include <soc/Ioh.h>
#include <soc/QuarkNcSocId.h>
enum {
@@ -27,6 +28,8 @@ enum {
SOC_UNIT_REGS,
RMU_TEMP_REGS,
MICROSECOND_DELAY,
+ LEG_GPIO_REGS,
+ GPIO_REGS,
};
enum {
@@ -38,6 +41,48 @@ enum {
_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \
size_, reg_, mask_, value_, timeout_, reg_set_)
+/* GPIO controller register access macros */
+#define REG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
+ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
+ GPIO_REGS)
+#define REG_GPIO_READ(reg_) \
+ REG_GPIO_ACCESS(READ, reg_, 0, 0, 0)
+#define REG_GPIO_WRITE(reg_, value_) \
+ REG_GPIO_ACCESS(WRITE, reg_, 0, value_, 0)
+#define REG_GPIO_AND(reg_, value_) \
+ REG_GPIO_RMW(reg_, value_, 0)
+#define REG_GPIO_RMW(reg_, mask_, value_) \
+ REG_GPIO_ACCESS(RMW, reg_, mask_, value_, 0)
+#define REG_GPIO_RXW(reg_, mask_, value_) \
+ REG_GPIO_ACCESS(RXW, reg_, mask_, value_, 0)
+#define REG_GPIO_OR(reg_, value_) \
+ REG_GPIO_RMW(reg_, 0xffffffff, value_)
+#define REG_GPIO_POLL(reg_, mask_, value_, timeout_) \
+ REG_GPIO_ACCESS(POLL, reg_, mask_, value_, timeout_)
+#define REG_GPIO_XOR(reg_, value_) \
+ REG_GPIO_RXW(reg_, 0xffffffff, value_)
+
+/* Legacy GPIO register access macros */
+#define REG_LEG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
+ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
+ LEG_GPIO_REGS)
+#define REG_LEG_GPIO_READ(reg_) \
+ REG_LEG_GPIO_ACCESS(READ, reg_, 0, 0, 0)
+#define REG_LEG_GPIO_WRITE(reg_, value_) \
+ REG_LEG_GPIO_ACCESS(WRITE, reg_, 0, value_, 0)
+#define REG_LEG_GPIO_AND(reg_, value_) \
+ REG_LEG_GPIO_RMW(reg_, value_, 0)
+#define REG_LEG_GPIO_RMW(reg_, mask_, value_) \
+ REG_LEG_GPIO_ACCESS(RMW, reg_, mask_, value_, 0)
+#define REG_LEG_GPIO_RXW(reg_, mask_, value_) \
+ REG_LEG_GPIO_ACCESS(RXW, reg_, mask_, value_, 0)
+#define REG_LEG_GPIO_OR(reg_, value_) \
+ REG_LEG_GPIO_RMW(reg_, 0xffffffff, value_)
+#define REG_LEG_GPIO_POLL(reg_, mask_, value_, timeout_) \
+ REG_LEG_GPIO_ACCESS(POLL, reg_, mask_, value_, timeout_)
+#define REG_LEG_GPIO_XOR(reg_, value_) \
+ REG_LEG_GPIO_RXW(reg_, 0xffffffff, value_)
+
/* RMU temperature register access macros */
#define REG_RMU_TEMP_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
@@ -105,10 +150,13 @@ enum {
#define REG_USB_XOR(reg_, value_) \
REG_USB_RXW(reg_, 0xffffffff, value_)
+void mainboard_gpio_init(void);
void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
uint32_t mdr_read(void);
void mdr_write(uint32_t value);
void mea_write(uint32_t reg_address);
+uint32_t reg_legacy_gpio_read(uint32_t reg_address);
+void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value);
uint32_t reg_rmu_temp_read(uint32_t reg_address);
#endif /* _QUARK_REG_ACCESS_H_ */
diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c
index be02340..48d5521 100644
--- a/src/soc/intel/quark/reg_access.c
+++ b/src/soc/intel/quark/reg_access.c
@@ -45,6 +45,56 @@ void mea_write(uint32_t reg_address)
& QNC_MEA_MASK);
}
+static uint32_t *get_gpio_address(uint32_t reg_address)
+{
+ uint32_t gpio_base_address;
+
+ /* Get the GPIO base address */
+ gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_1);
+ gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+ ASSERT (gpio_base_address != 0x00000000);
+
+ /* Return the GPIO register address */
+ return (uint32_t *)(gpio_base_address + reg_address);
+}
+
+static uint32_t reg_gpio_read(uint32_t reg_address)
+{
+ /* Read the GPIO register */
+ return *get_gpio_address(reg_address);
+}
+
+static void reg_gpio_write(uint32_t reg_address, uint32_t value)
+{
+ /* Write the GPIO register */
+ *get_gpio_address(reg_address) = value;
+}
+
+static uint16_t get_legacy_gpio_address(uint32_t reg_address)
+{
+ uint32_t gpio_base_address;
+
+ /* Get the GPIO base address */
+ gpio_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GBA_BASE);
+ ASSERT (gpio_base_address >= 0x80000000);
+ gpio_base_address &= B_QNC_LPC_GPA_BASE_MASK;
+
+ /* Return the GPIO register address */
+ return (uint16_t)(gpio_base_address + reg_address);
+}
+
+uint32_t reg_legacy_gpio_read(uint32_t reg_address)
+{
+ /* Read the legacy GPIO register */
+ return inl(get_legacy_gpio_address(reg_address));
+}
+
+void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value)
+{
+ /* Write the legacy GPIO register */
+ outl(value, get_legacy_gpio_address(reg_address));
+}
+
uint32_t reg_rmu_temp_read(uint32_t reg_address)
{
/* Read the RMU temperature register */
@@ -110,6 +160,16 @@ static uint64_t reg_read(struct reg_script_context *ctx)
ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
return 0;
+ case GPIO_REGS:
+ ctx->display_prefix = "GPIO: ";
+ value = reg_gpio_read(step->reg);
+ break;
+
+ case LEG_GPIO_REGS:
+ ctx->display_prefix = "Legacy GPIO: ";
+ value = reg_legacy_gpio_read(step->reg);
+ break;
+
case RMU_TEMP_REGS:
ctx->display_prefix = "RMU TEMP";
value = reg_rmu_temp_read(step->reg);
@@ -140,6 +200,16 @@ static void reg_write(struct reg_script_context *ctx)
ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
return;
+ case GPIO_REGS:
+ ctx->display_prefix = "GPIO: ";
+ reg_gpio_write(step->reg, (uint32_t)step->value);
+ break;
+
+ case LEG_GPIO_REGS:
+ ctx->display_prefix = "Legacy GPIO: ";
+ reg_legacy_gpio_write(step->reg, (uint32_t)step->value);
+ break;
+
case RMU_TEMP_REGS:
ctx->display_prefix = "RMU TEMP";
reg_rmu_temp_write(step->reg, (uint32_t)step->value);
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