[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Take advantage of common opregion code
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Fri May 13 20:23:08 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14807
-gerrit
commit 4483fbd88b18115682e356b1e4acf3c12aa24b8d
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Thu May 12 19:11:48 2016 -0700
soc/intel/apollolake: Take advantage of common opregion code
Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/soc/intel/apollolake/Kconfig | 1 +
src/soc/intel/apollolake/graphics.c | 47 +++++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 41a96c9..3fb0c8b 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -44,6 +44,7 @@ config CPU_SPECIFIC_OPTIONS
select PLATFORM_USES_FSP2_0
select HAVE_HARD_RESET
select SOC_INTEL_COMMON
+ select SOC_INTEL_COMMON_GFX_OPREGION
config TPM_ON_FAST_SPI
bool
diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c
index 2384062..f326b5b 100644
--- a/src/soc/intel/apollolake/graphics.c
+++ b/src/soc/intel/apollolake/graphics.c
@@ -15,12 +15,15 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
#include <console/console.h>
#include <fsp/util.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/pci_ids.h>
+#include <soc/intel/common/opregion.h>
static uintptr_t framebuffer_bar = (uintptr_t)NULL;
@@ -53,11 +56,55 @@ static void igd_set_resources(struct device *dev)
pci_dev_set_resources(dev);
}
+static unsigned long igd_write_opregion(device_t dev, unsigned long current,
+ struct acpi_rsdp *rsdp)
+{
+ igd_opregion_t *opregion;
+ uint16_t reg16;
+
+ printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
+ opregion = (igd_opregion_t *)current;
+
+ if (init_igd_opregion(opregion))
+ current += sizeof(igd_opregion_t);
+
+ /* TODO Initialize Mailbox 3 */
+ opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
+ opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
+ opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
+ opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
+ opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
+ opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
+ opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
+ opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
+ opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
+ opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
+ opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
+ opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
+ opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
+ opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
+ opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
+
+ /*
+ * TODO This needs to happen in S3 resume, too.
+ * Maybe it should move to the finalize handler.
+ */
+
+ pci_write_config32(dev, ASLS, (uintptr_t)opregion);
+ reg16 = pci_read_config16(dev, SWSCI);
+ reg16 &= ~(1 << 0);
+ reg16 |= (1 << 15);
+ pci_write_config16(dev, SWSCI, reg16);
+
+ return acpi_align_current(current);
+}
+
static const struct device_operations igd_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = igd_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = pci_dev_init,
+ .write_acpi_tables = igd_write_opregion,
.enable = DEVICE_NOOP
};
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