[coreboot-gerrit] New patch to review for coreboot: x60: restyle _CST table, add C4 state

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14801

-gerrit

commit 498e5a8ae9c5384ca6648ace0180fe896976d28b
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Fri May 13 00:07:36 2016 +0200

    x60: restyle _CST table, add C4 state
    
    First of all requesting low power acpi c-states
    has two software interfaces:
    Using P_LVLx I/O reads or using equivalent MWAIT requersts.
    Since newer intel boards in coreboot use MWAIT, I tried to
    make the x60 c-states consistent with that.
    
    The C4 state is a lower power state that is only entered
    when both cores request it, else the core remains in C3.
    The power and latency are arbitrary but according to
    documentation the OS is supposed to handle this fine.
    
    In practice the x60 seems not to use noticable less power
    with c4 enabled.
    
    TEST= Build and boot platform. See if there is a state4
    in /sys/devices/system/cpu/cpu0/cpuidle/
    
    Change-Id: I9eeb5b008e2ddc2193725667f2c13582a4877e3c
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/mainboard/lenovo/x60/mainboard.c | 39 +++++++++++++++++++++++++++++++++---
 1 file changed, 36 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
index 5ea4221..1db44f5 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -38,10 +38,43 @@
 
 #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT
 
+#define MWAIT_RES(state, sub_state)                         \
+	{                                                   \
+	  .space_id = ACPI_ADDRESS_SPACE_FIXED,		    \
+	  .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,          \
+	  .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,          \
+	  {						    \
+		  .resv = 0,				    \
+	  },						    \
+	  .addrl = (((state) << 4) | (sub_state)),          \
+	  .addrh = 0,                                       \
+	}
+
 static acpi_cstate_t cst_entries[] = {
-	{ 1,  1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
-	{ 2,  1,  500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
-	{ 2, 17,  250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
+	{
+		.ctype = 1,
+		.latency = 1,
+		.power = 1000,
+		.resource = MWAIT_RES(0, 0),
+	},
+	{
+		.ctype = 2,
+		.latency = 1,
+		.power = 500,
+		.resource = MWAIT_RES(1, 0),
+	},
+	{
+		.ctype = 3,
+		.latency = 17,
+		.power = 250,
+		.resource = MWAIT_RES(2, 0),
+	},
+	{
+		.ctype = 3,
+		.latency = 34,
+		.power = 200,
+		.resource = MWAIT_RES(3, 0),
+	},
 };
 
 int get_cst_entries(acpi_cstate_t **entries)