[coreboot-gerrit] New patch to review for coreboot: ec/google/chromeec: provide way to query ioport resources

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14769

-gerrit

commit 84823507587d5f42377f59e68f46b967b7e1c9d8
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue May 10 17:00:06 2016 -0500

    ec/google/chromeec: provide way to query ioport resources
    
    In order to provide other stages access to the ioport ranges
    required by the ChromeEC provide agoogle_chromeec_ioport_resources()
    function to fill in the details. Currently, the ioport resources are
    only consumed by the LPC implemenation. Also allow ec_lpc.c to be built
    for the bootblock stage.
    
    Change-Id: I6c181b42e80e71fe07e8fa90df783107287f16ad
    Signed-off-by: Aaron Durbin  <adurbin at chromium.org>
---
 src/ec/google/chromeec/Makefile.inc |  1 +
 src/ec/google/chromeec/ec.h         |  3 +++
 src/ec/google/chromeec/ec_lpc.c     | 36 +++++++++++++++++++++++++-----------
 3 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc
index 759c0da..7ae1835 100644
--- a/src/ec/google/chromeec/Makefile.inc
+++ b/src/ec/google/chromeec/Makefile.inc
@@ -1,5 +1,6 @@
 ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC),y)
 
+bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
 ramstage-y += ec.c crosec_proto.c vstore.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 85f41ad..d9279b8 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -21,6 +21,9 @@
 #include <stdint.h>
 #include "ec_commands.h"
 
+/* Fill in base and size of the IO port resources used. */
+void google_chromeec_ioport_resources(uint16_t *base, size_t *size);
+
 #ifndef __PRE_RAM__
 int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen,
 			     uint8_t *buffer, int len, int is_read);
diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c
index f9d0f8b..cae349d 100644
--- a/src/ec/google/chromeec/ec_lpc.c
+++ b/src/ec/google/chromeec/ec_lpc.c
@@ -367,6 +367,26 @@ uint8_t google_chromeec_get_switches(void)
 	return read_byte(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
 }
 
+void google_chromeec_ioport_resources(uint16_t *out_base, size_t *out_size)
+{
+	uint16_t base;
+	size_t size;
+
+	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) {
+		base = MEC_EMI_BASE;
+		size = MEC_EMI_SIZE;
+	} else {
+		base = EC_HOST_CMD_REGION0;
+		size = 2 * EC_HOST_CMD_REGION_SIZE;
+		/* Make sure MEMMAP region follows host cmd region. */
+		assert(base + size == EC_LPC_ADDR_MEMMAP);
+		size += EC_MEMMAP_SIZE;
+	}
+
+	*out_base = base;
+	*out_size = size;
+}
+
 #ifdef __PRE_RAM__
 
 int google_chromeec_command(struct chromeec_command *cec_command)
@@ -423,19 +443,13 @@ static void lpc_ec_read_resources(struct device *dev)
 {
 	unsigned int idx = 0;
 	struct resource * res;
+	uint16_t base;
+	size_t size;
 
-
+	google_chromeec_ioport_resources(&base, &size);
 	res = new_resource(dev, idx++);
-	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) {
-		res->base = MEC_EMI_BASE;
-		res->size = MEC_EMI_SIZE;
-	} else {
-		res->base = EC_HOST_CMD_REGION0;
-		res->size = 2 * EC_HOST_CMD_REGION_SIZE;
-		/* Make sure MEMMAP region follows host cmd region. */
-		assert(res->base + res->size == EC_LPC_ADDR_MEMMAP);
-		res->size +=  EC_MEMMAP_SIZE;
-	}
+	res->base = base;
+	res->size = size;
 	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }