[coreboot-gerrit] Patch set updated for coreboot: google/gale: Remove some unwanted code

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14674

-gerrit

commit 8ec71032f4fc77d6a64b98e9d5c75690deac2de9
Author: Varadarajan Narayanan <varada at codeaurora.org>
Date:   Wed Nov 25 14:26:01 2015 +0530

    google/gale: Remove some unwanted code
    
    BUG=chrome-os-partner:49249
    TEST=Compiles and boots
    BRANCH=none
    
    Original-Commit-Id: 96a125f99af3eaa8931563fa74ccef8dd997f3ca
    Original-Change-Id: Iebfe7429c400e7119510a51c3124d432f00af76d
    Original-Signed-off-by: Varadarajan Narayanan <varada at codeaurora.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/333319
    Original-Commit-Ready: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    
    squashed:
    
    soc/qualcomm/ipq40xx: Add function to reset TPM
    
    BUG=chrome-os-partner:49249
    TEST=Able to read TPM registers
    BRANCH=none
    
    Original-Commit-Id: 9df3e9dfe61382143394a58a3a927c05a875b377
    Original-Change-Id: I38732acc4418c94b88a430ba697db4e3b145c341
    Original-Signed-off-by: Varadarajan Narayanan <varada at codeaurora.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/333317
    Original-Commit-Ready: David Hendricks <dhendrix at chromium.org>
    Original-Tested-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    
    Change-Id: Ifc8df3b7e231eef944efec3a6f973b402c11bcaf
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 src/mainboard/google/gale/chromeos.c  |  2 +
 src/mainboard/google/gale/mainboard.c | 73 +++++++++++++++--------------------
 2 files changed, 34 insertions(+), 41 deletions(-)

diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c
index d01fbbe..c4af048 100644
--- a/src/mainboard/google/gale/chromeos.c
+++ b/src/mainboard/google/gale/chromeos.c
@@ -78,8 +78,10 @@ enum switch_state {
 
 static void display_pattern(int pattern)
 {
+#if IS_ENABLED(notyet)
 	if (board_id() == BOARD_ID_WHIRLWIND_SP5)
 		ww_ring_display_pattern(GSBI_ID_7, pattern);
+#endif
 }
 
 #define WIPEOUT_MODE_DELAY_MS (8 * 1000)
diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c
index 9d99a2c..a8117af 100644
--- a/src/mainboard/google/gale/mainboard.c
+++ b/src/mainboard/google/gale/mainboard.c
@@ -31,62 +31,53 @@
 
 static void setup_usb(void)
 {
-#if !CONFIG_BOARD_VARIANT_AP148
-	gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO,
-			     GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE);
-	gpio_set(USB_ENABLE_GPIO, 1);
-#endif
 	usb_clock_config();
 
 	setup_usb_host1();
 }
 
-#define TPM_RESET_GPIO 22
-static void setup_tpm(void)
+#define TPM_RESET_GPIO		19
+static void ipq_setup_tpm(void)
 {
-	if (board_id() != BOARD_ID_PROTO_0)
-		return; /* Only proto0 have TPM reset connected to GPIO22 */
-
-	gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP,
-			     GPIO_4MA, GPIO_ENABLE);
-	/*
-	 * Generate a reset pulse. The spec calls for 80 us minimum, let's
-	 * make it twice as long. If the output was driven low originally, the
-	 * reset pulse will be even longer.
-	 */
+#ifdef CONFIG_I2C_TPM
+	gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO,
+			     GPIO_PULL_UP, GPIO_6MA, 1);
 	gpio_set(TPM_RESET_GPIO, 0);
-	udelay(160);
+	udelay(100);
 	gpio_set(TPM_RESET_GPIO, 1);
-}
-
-#define SW_RESET_GPIO 26
-static void assert_sw_reset(void)
-{
-	if (board_id() == BOARD_ID_PROTO_0)
-		return;
 
 	/*
-	 * only proto0.2 and later care about this. We want to keep the
-	 * ethernet switch in reset, otherwise it comes up in default
-	 * (bridging) mode.
+	 * ----- Per the SLB 9615XQ1.2 spec -----
+	 *
+	 * 4.7.1 Reset Timing
+	 *
+	 * The TPM_ACCESS_x.tpmEstablishment bit has the correct value
+	 * and the TPM_ACCESS_x.tpmRegValidSts bit is typically set
+	 * within 8ms after RESET# is deasserted.
+	 *
+	 * The TPM is ready to receive a command after less than 30 ms.
+	 *
+	 * --------------------------------------
+	 *
+	 * I'm assuming this means "wait for 30ms"
+	 *
+	 * If we don't wait here, subsequent QUP I2C accesses
+	 * to the TPM either fail or timeout.
 	 */
-	gpio_tlmm_config_set(SW_RESET_GPIO, FUNC_SEL_GPIO,
-			     GPIO_PULL_UP, GPIO_4MA, GPIO_ENABLE);
+	mdelay(30);
 
-	gpio_set(SW_RESET_GPIO, 1);
+#endif /* CONFIG_I2C_TPM */
 }
 
 static void mainboard_init(device_t dev)
 {
-	 /* disable mmu and d-cache before setting up secure world.*/
-	 dcache_mmu_disable();
-	 start_tzbsp();
-	 /* Setup mmu and d-cache again as non secure entries. */
-	 setup_mmu(DRAM_INITIALIZED);
-	 start_rpm();
-	 setup_usb();
-	 assert_sw_reset();
-	 setup_tpm();
+	/* disable mmu and d-cache before setting up secure world.*/
+	dcache_mmu_disable();
+	start_tzbsp();
+	/* Setup mmu and d-cache again as non secure entries. */
+	setup_mmu(DRAM_INITIALIZED);
+	setup_usb();
+	ipq_setup_tpm();
 
 #if IS_ENABLED(CONFIG_CHROMEOS)
 	/* Copy WIFI calibration data into CBMEM. */
@@ -99,7 +90,7 @@ static void mainboard_init(device_t dev)
 	 *
 	 * 48000 * 2 * 16 * 4 = 6144000
 	 */
-	audio_clock_config(6144000);
+	//audio_clock_config(6144000);
 }
 
 static void mainboard_enable(device_t dev)