[coreboot-gerrit] Patch set updated for coreboot: soc/qualcomm/ipq40xx: Update memory map to align to ipq40xx

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14654

-gerrit

commit c797d721286bd39f1c4b5ed74b41fcc0378428c7
Author: Varadarajan Narayanan <varada at codeaurora.org>
Date:   Thu Mar 17 14:37:56 2016 +0530

    soc/qualcomm/ipq40xx: Update memory map to align to ipq40xx
    
    Update the memory to map to align with the internal memory region
    map of IPQ40XX
    
    BUG=chrome-os-partner:49249
    TEST=None. Initial code not sure if it will even compile
    BRANCH=none
    
    Change-Id: Iea40484751a1c0439ed511319ef09a0254eba757
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e33712a729ef9831508c2e9aae81d0b32495b681
    Original-Change-Id: Iba1c5281a2fbda4ab96126676b901ba71f6b28e0
    Original-Signed-off-by: Varadarajan Narayanan <varada at codeaurora.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/333295
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
 src/mainboard/google/gale/bootblock.c             |  4 +-
 src/mainboard/google/gale/mmu.c                   | 13 +++---
 src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld | 55 ++++++++++++++---------
 3 files changed, 44 insertions(+), 28 deletions(-)

diff --git a/src/mainboard/google/gale/bootblock.c b/src/mainboard/google/gale/bootblock.c
index 8313501..63167cc 100644
--- a/src/mainboard/google/gale/bootblock.c
+++ b/src/mainboard/google/gale/bootblock.c
@@ -40,8 +40,8 @@ void bootblock_mainboard_init(void)
 
 	setup_mmu(DRAM_NOT_INITIALIZED);
 
-	if (((uintptr_t)maskrom_param < (uintptr_t)&_sram) ||
-	    ((uintptr_t)maskrom_param > (uintptr_t)&_esram)) {
+	if (((uintptr_t)maskrom_param < (uintptr_t)&_wifi_imem_0) ||
+	    ((uintptr_t)maskrom_param > (uintptr_t)&_ewifi_imem_0)) {
 		printk(BIOS_INFO, "No uber-sbl parameter detected\n");
 		return;
 	}
diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c
index 4d2e9a0..c3b9f0f 100644
--- a/src/mainboard/google/gale/mmu.c
+++ b/src/mainboard/google/gale/mmu.c
@@ -45,14 +45,19 @@ void setup_mmu(enum dram_state dram)
 {
 	dcache_mmu_disable();
 
+	mmu_init();
+
 	/* start with mapping everything as strongly ordered. */
 	mmu_config_range(0, 4096, DCACHE_OFF);
 
 	/* Map Device memory. */
-	mmu_config_range_kb(RPM_START, RPM_SIZE, DCACHE_OFF);
+	mmu_config_range_kb(WIFI_IMEM_0_START,
+				WIFI_IMEM_0_END - WIFI_IMEM_0_START,
+				DCACHE_WRITEBACK);
 
-	mmu_config_range_kb(SRAM_START, SRAM_END - SRAM_START,
-		DCACHE_WRITEBACK);
+	mmu_config_range_kb(WIFI_IMEM_1_START,
+				WIFI_IMEM_1_END - WIFI_IMEM_1_START,
+				DCACHE_WRITEBACK);
 
 	/* Map DRAM memory */
 	setup_dram_mappings(dram);
@@ -62,7 +67,5 @@ void setup_mmu(enum dram_state dram)
 	/* disable Page 0 for trapping NULL pointer references. */
 	mmu_disable_range_kb(0, 1);
 
-	mmu_init();
-
 	dcache_mmu_enable();
 }
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
index 6ff2b77..8baf1b0 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
@@ -18,30 +18,43 @@
 
 #include <arch/header.ld>
 
+#define REGION_START(name, addr)	SYMBOL(name, addr)
+#define REGION_END(name, addr)		SYMBOL(e##name, addr)
+
 SECTIONS
 {
-	REGION(rpm, 0x00020000,  160K, 8K)
-	SRAM_START(0x2A000000)
+	REGION(oc_imem, 0x08600000, 32K, 0)
+
+	/* ==vvv== OC_IMEM_1_START	0x08600000 ==vvv== */
+/*	DDR(0x08600000, 32K) */
+	/* ==^^^== OC_IMEM_1_END	0x08608000 ==^^^== */
+
+	/* ==vvv== WIFI_IMEM_0_START	0x0A0C0000 ==vvv== */
+	REGION_START(wifi_imem_0, 0x0A0C0000)
 	/* This includes bootblock image, can be reused after bootblock starts */
-/*	UBER_SBL(0x2A000000, 48K) */
-/*	DDR(0x2A000000, 48K) */
-	BOOTBLOCK(0x2A00C000, 24K)
-	OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K)
-	VBOOT2_WORK(0x2A022000, 16K)
-	PRERAM_CBMEM_CONSOLE(0x2A026000, 32K)
-	TIMESTAMP(0x2A02E000, 1K)
-
-/*	0x2e400..0x3F000  67 KB free */
-
-/* Keep the below area reserved at all times, it is used by various QCA
-   components as shared data
-	QCA_SHARED_RAM(2A03F000, 4K)
-*/
-	STACK(0x2A040000, 16K)
-	PRERAM_CBFS_CACHE(0x2A044000, 93K)
-	TTB_SUBTABLES(0x2A05B800, 2K)
-	TTB(0x2A05C000, 16K)
-	SRAM_END(0x2A060000)
+/*	UBER_SBL(0x0A0C0000, 48K) */
+
+	PRERAM_CBFS_CACHE(0x0A0C0000, 93K)
+
+	TTB_SUBTABLES(0x0A0E0000, 4K)
+	TTB(0x0A0F0000, 16K)
+	REGION_END(wifi_imem_0, 0x0A100000)
+	/* ==^^^== WIFI_IMEM_0_END	0x0A100000 ==^^^== */
+
+
+	/* ==vvv== WIFI_IMEM_1_START	0x0A8C0000 ==vvv== */
+	REGION_START(wifi_imem_1, 0x0A8C0000)
+	BOOTBLOCK(0x0A8C0000, 24K)
+	OVERLAP_VERSTAGE_ROMSTAGE(0x0A8C6000, 64K)
+	VBOOT2_WORK(0x0A8D6000, 16K)
+	PRERAM_CBMEM_CONSOLE(0x0A8DA000, 32K)
+	TIMESTAMP(0x0A8E2000, 1K)
+
+/*	0x0A8E2400..0x0A8FC000  103 KB free */
+
+	STACK(0x0A8FC000, 16K)
+	REGION_END(wifi_imem_1, 0x0A900000)
+	/* ==^^^== WIFI_IMEM_1_END	0x0A900000 ==^^^== */
 
 	DRAM_START(0x40000000)
 	RAMSTAGE(0x40640000, 128K)