[coreboot-gerrit] Patch set updated for coreboot: soc/intel/quark: Identify the console UART

[Leroy P Leahy (leroy.p.leahy@intel.com)]

Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14610

-gerrit

commit 66ec51130d730385e8bc58969e52b260d966cb13
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Wed May 4 12:50:51 2016 -0700

    soc/intel/quark: Identify the console UART
    
    Pass the UART identifier to CorebootPayloadPkg
    
    Testing on Galileo:
    *  Edit the src/mainboard/intel/galileo/Makefile.inc file:
       *  Add "select ADD_FSP_PDAT_FILE"
       *  Add "select ADD_FSP_RAW_BIN"
       *  Add "select ADD_RMU_FILE"
    *  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
    *  Place the pdat.bin files in the location specified by
       CONFIG_FSP_PDAT_FILE
    *  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
    *  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
       UEFIPAYLOAD.fd
    *  Testing is successful when CorebootPayloadPkg is able to properly
       initialize the serial port without using built-in values.
    
    Change-Id: I9db1c31c3544d56b66f5a79ac8c3acee41788983
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/soc/intel/quark/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 8485aa3..ae25c32 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -60,6 +60,13 @@ config TTYS0_LCS
 	depends on ENABLE_BUILTIN_HSUART1
 	default 3
 
+# Console: PCI UART bus 0 << 20, device 20 << 15, function 5 << 12
+#          Valid bit, PCI UART in use: 1 << 31
+config UART_PCI_ADDR
+	hex
+	depends on ENABLE_BUILTIN_HSUART1
+	default 0x800a5000
+
 #####
 # Debug support
 #     The following options provide debug support for the Quark coreboot