[coreboot-gerrit] Patch set updated for coreboot: coreboot_tables: Extend serial port description
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Mon May 9 16:27:26 CEST 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14609
-gerrit
commit 1cc4cc606fabf4e267ba476c2964f356593e9255
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Wed May 4 11:59:19 2016 -0700
coreboot_tables: Extend serial port description
Extend the serial port description to include the input clock frequency
and a payload specific value.
Without the input frequency it is impossible for the payload to compute
the baud-rate divisor without making an assumption about the frequency.
This breaks down when the UART is able to support multiple input clock
frequencies.
Add the UART_PCI_ADDR Kconfig value to specify the unique PCI device
being used as the console UART. Specify this value as zero when the
UART is not on the PCI bus. Otherwise specify the device using bus,
device and function along with setting the valid bit.
Currently the only payload to consume these new fields is the EDK-II
CorebootPayloadPkg.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Testing is successful when CorebootPayloadPkg is able to properly
initialize the serial port without using built-in values.
Change-Id: Id4b4455bbf9583f0d66c315d38c493a81fd852a8
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
payloads/libpayload/include/coreboot_tables.h | 15 +++++++++++++++
src/commonlib/include/commonlib/coreboot_tables.h | 15 +++++++++++++++
src/drivers/uart/Kconfig | 17 +++++++++++++++++
src/drivers/uart/oxpcie_early.c | 5 +++++
src/drivers/uart/pl011.c | 5 +++++
src/drivers/uart/uart8250io.c | 5 +++++
src/drivers/uart/uart8250mem.c | 5 +++++
src/lib/coreboot_table.c | 2 ++
8 files changed, 69 insertions(+)
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 276f25f..d77242a 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -121,6 +121,21 @@ struct cb_serial {
u32 baseaddr;
u32 baud;
u32 regwidth;
+
+ /* Crystal or input frequency to the chip containing the UART.
+ * Provide the board specific details to allow the payload to
+ * initialize the chip containing the UART and make independent
+ * decisions as to which dividers to select and their values
+ * to eventually arrive at the desired console baud-rate. */
+ u32 input_hertz;
+
+ /* UART PCI address: bus, device, function
+ * 1 << 31 - Valid bit, PCI UART in use
+ * Bus << 20
+ * Device << 15
+ * Function << 12
+ */
+ u32 uart_pci_addr;
};
#define CB_TAG_CONSOLE 0x00010
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 5c28791..7d58fdd 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -173,6 +173,21 @@ struct lb_serial {
uint32_t baseaddr;
uint32_t baud;
uint32_t regwidth;
+
+ /* Crystal or input frequency to the chip containing the UART.
+ * Provide the board specific details to allow the payload to
+ * initialize the chip containing the UART and make independent
+ * decisions as to which dividers to select and their values
+ * to eventually arrive at the desired console baud-rate. */
+ uint32_t input_hertz;
+
+ /* UART PCI address: bus, device, function
+ * 1 << 31 - Valid bit, PCI UART in use
+ * Bus << 20
+ * Device << 15
+ * Function << 12
+ */
+ uint32_t uart_pci_addr;
};
#define LB_TAG_CONSOLE 0x0010
diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig
index f4ad011..ae3e81a 100644
--- a/src/drivers/uart/Kconfig
+++ b/src/drivers/uart/Kconfig
@@ -41,3 +41,20 @@ config DRIVERS_UART_PL011
bool
default n
select HAVE_UART_SPECIAL
+
+config UART_USE_REFCLK_AS_INPUT_CLOCK
+ bool
+ default n
+ help
+ Use uart_platform_refclk to specify the input clock value.
+
+config UART_PCI_ADDR
+ hex "UART's PCI bus, device, function address"
+ default 0
+ help
+ Specify zero if the UART is connected to another bus type.
+ For PCI based UARTs, build the value as:
+ * 1 << 31 - Valid bit, PCI UART in use
+ * Bus << 20
+ * Device << 15
+ * Function << 12
diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c
index eb91d31..6582a9e 100644
--- a/src/drivers/uart/oxpcie_early.c
+++ b/src/drivers/uart/oxpcie_early.c
@@ -92,6 +92,11 @@ void uart_fill_lb(void *data)
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
serial.regwidth = 1;
+ if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK))
+ serial.input_hertz = uart_platform_refclk();
+ else
+ serial.input_hertz = 0;
+ serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c
index aa55c68..808cb46 100644
--- a/src/drivers/uart/pl011.c
+++ b/src/drivers/uart/pl011.c
@@ -48,6 +48,11 @@ void uart_fill_lb(void *data)
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
serial.regwidth = 1;
+ if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK))
+ serial.input_hertz = uart_platform_refclk();
+ else
+ serial.input_hertz = 0;
+ serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
index 63bc42f..0974005 100644
--- a/src/drivers/uart/uart8250io.c
+++ b/src/drivers/uart/uart8250io.c
@@ -139,6 +139,11 @@ void uart_fill_lb(void *data)
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
serial.regwidth = 1;
+ if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK))
+ serial.input_hertz = uart_platform_refclk();
+ else
+ serial.input_hertz = 0;
+ serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data);
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
index 278ddb8..2f2bd2d 100644
--- a/src/drivers/uart/uart8250mem.c
+++ b/src/drivers/uart/uart8250mem.c
@@ -156,6 +156,11 @@ void uart_fill_lb(void *data)
serial.regwidth = sizeof(uint32_t);
else
serial.regwidth = sizeof(uint8_t);
+ if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK))
+ serial.input_hertz = uart_platform_refclk();
+ else
+ serial.input_hertz = 0;
+ serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 4dbac19..3af2be6 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -119,6 +119,8 @@ void lb_add_serial(struct lb_serial *new_serial, void *data)
serial->baseaddr = new_serial->baseaddr;
serial->baud = new_serial->baud;
serial->regwidth = new_serial->regwidth;
+ serial->input_hertz = new_serial->input_hertz;
+ serial->uart_pci_addr = new_serial->uart_pci_addr;
}
void lb_add_console(uint16_t consoletype, void *data)
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