[coreboot-gerrit] Patch merged into coreboot/master: google/gru: enable pp1500 and pp3000 rails as soon as possible

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 591298a575d6815346c312bb5254f77abef56fb8
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Apr 22 16:06:26 2016 -0700

    google/gru: enable pp1500 and pp3000 rails as soon as possible
    
    The idea is that they stay low unless we know that we booted from SPI
    flash. As this code runs in SPI flash - it is ok to turn these rails
    on as soon as possible, and pp3000 rail it is essential for UART to
    work.
    
    Kevin rev1 and Gru designs are going to be using these pins to
    control these rails. Kevin rev1 had those GPIO pins routed to two
    chip enable signals, it is save to assert them high.
    
    BRANCH=none
    BUG=chrome-os-partner:51537
    TEST=kevin rev0 still boots (which does not prove much)
    TEST=run coreboot on kevin rev1 to kernel
    
    Change-Id: I5f3eb4cf5d6f04a0253574dd8b5c039eab0bae1a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 987042246672e9391087dbd5060785a379dde131
    Original-Change-Id: I31bb03334ad9e3aa57db726fb43dec85014a3f05
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/341543
    Original-Tested-by: Shunqian Zheng <zhengsq at rock-chips.com>
    Reviewed-on: https://review.coreboot.org/14729
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See https://review.coreboot.org/14729 for details.

-gerrit