[coreboot-gerrit] Patch merged into coreboot/master: rockchip: rk3399: support saradc

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit bf48fbbcc116b79fa5bfe05db83c354ee87e3843
Author: Lin Huang <hl at rock-chips.com>
Date:   Wed Mar 23 19:24:53 2016 +0800

    rockchip: rk3399: support saradc
    
    This patch add functions to configure saradc clk and get
    saradc's raw value for each channel.
    
    Currently add saradc to ramstage.
    
    Please refer to TRM V0.3 Part 2 Chapter 18 for this IP.
    
    BRANCH=none
    BUG=chrome-os-partner:51537
    TEST=on kevin board, get the raw value 61 for channel 0,
         measure the ADC_IN0 as 0.109V,
         61.0/1024 = 0.05957  0.109V/1.8V = 0.06056
    
    Change-Id: Ic198b2a964ccf8bb687441f0e2702665402fff6e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: bc400316de2d75eccad3990a4187bf2dc49a844a
    Original-Change-Id: I542430ed97bd27f9bfcec89b1d703d9fa390d4e0
    Original-Signed-off-by: Lin Huang <hl at rock-chips.com>
    Original-Signed-off-by: Shunqian Zheng <zhengsq at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/334177
    Original-Commit-Ready: Vadim Bendebury <vbendeb at chromium.org>
    Original-Tested-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
    Reviewed-on: https://review.coreboot.org/14720
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See https://review.coreboot.org/14720 for details.

-gerrit