[coreboot-gerrit] Patch set updated for coreboot: soc/qualcomm/ipq40xx: Enable crashdump handling
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Sat May 7 10:39:58 CEST 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14679
-gerrit
commit 20a29f34480345c28d7ee6f9fadffd6079cc8bb6
Author: Varadarajan Narayanan <varada at codeaurora.org>
Date: Wed Jan 6 14:13:25 2016 +0530
soc/qualcomm/ipq40xx: Enable crashdump handling
Clear the crash dump cookie set by SBL to indicate that
it is a normal reset.
Inform DDR image of the entrypoint for SDI image to be
preserved in OCIMEM which will be needed during watchdog
resets.
BUG=chrome-os-partner:49249
TEST=DDR image is able to fetch the entry point address
BRANCH=none
Change-Id: I3e6e4a108585bb257e3ad02956c420acbcb2554e
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: bd726256a5ae89672810b57e1d2a7a9287f60627
Original-Change-Id: Id6e09516209f47c3ea8fa3d8d90440789b395660
Original-Signed-off-by: Varadarajan Narayanan <varada at codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333321
Original-Commit-Ready: David Hendricks <dhendrix at chromium.org>
Original-Tested-by: David Hendricks <dhendrix at chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
src/mainboard/google/gale/reset.c | 7 ++
src/soc/qualcomm/ipq40xx/blobs_init.c | 108 ++++++++++++---------------
src/soc/qualcomm/ipq40xx/include/soc/iomap.h | 3 +
3 files changed, 56 insertions(+), 62 deletions(-)
diff --git a/src/mainboard/google/gale/reset.c b/src/mainboard/google/gale/reset.c
index 47a46d4..d37051a 100644
--- a/src/mainboard/google/gale/reset.c
+++ b/src/mainboard/google/gale/reset.c
@@ -21,5 +21,12 @@
void hard_reset(void)
{
+ /*
+ * At boot time the boot loaders would have set a magic cookie
+ * here to detect watchdog reset. However, since this is a
+ * normal reset clear the magic numbers.
+ */
+ write32(TCSR_BOOT_MISC_DETECT, 0);
+ write32(TCSR_RESET_DEBUG_SW_ENTRY, 0);
write32(GCNT_PSHOLD, 0);
}
diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c
index 5b19fc1..77c0289 100644
--- a/src/soc/qualcomm/ipq40xx/blobs_init.c
+++ b/src/soc/qualcomm/ipq40xx/blobs_init.c
@@ -20,12 +20,19 @@
#include <console/console.h>
#include <string.h>
#include <timer.h>
+#include <timestamp.h>
+#include <program_loading.h>
#include <soc/iomap.h>
#include <soc/soc_services.h>
#include "mbn_header.h"
+struct cdt_info {
+ uint32_t size; /* size of the whole table */
+ uint8_t *cdt_ptr; /* pointer to CDT */
+};
+
static void *load_ipq_blob(const char *file_name)
{
struct mbn_header *blob_mbn;
@@ -43,6 +50,7 @@ static void *load_ipq_blob(const char *file_name)
return NULL;
blob_dest = (void *) blob_mbn->mbn_destination;
+
if (blob_mbn->mbn_destination) {
/* Copy the blob to the appropriate memory location. */
memcpy(blob_dest, blob_mbn + 1, blob_mbn->mbn_total_size);
@@ -50,25 +58,41 @@ static void *load_ipq_blob(const char *file_name)
return blob_dest;
}
- /*
- * The blob did not have to be relocated, return its address in CBFS
- * cache.
- */
- return blob_mbn + 1;
+ return blob_mbn;
}
#ifdef __PRE_RAM__
-#define DDR_VERSION() ((const char *)0x2a03f600)
+#define DDR_VERSION() ((const char *)"private build")
#define MAX_DDR_VERSION_SIZE 48
+typedef struct {
+ uint64_t entry_point; /* Write only for Core Boot */
+ uint32_t elf_class;
+} sys_debug_qsee_info_type_t;
+
+typedef struct {
+ sys_debug_qsee_info_type_t *qsee_info;
+ uint64_t sdi_entry; /* Read only for Core Boot */
+} sbl_rw_ret_info_t;
+
+sbl_rw_ret_info_t *sbl_rw_ret_info;
+
int initialize_dram(void)
{
- void *cdt;
- int (*ddr_init_function)(void *cdt_header);
+ struct mbn_header *cdt;
+ struct cdt_info cdt_header;
+ uint32_t sw_entry;
+ /*
+ * FIXME: Hard coding the address. Have to somehow get it
+ * automatically
+ */
+ void *tzbsp = (uint8_t *)0x87e80000;
- cdt = load_ipq_blob("cdt.mbn");
- ddr_init_function = load_ipq_blob("ddr.mbn");
+ sbl_rw_ret_info_t (*(*ddr_init_function)(struct cdt_info *cdt_header));
+
+ cdt = load_ipq_blob(CONFIG_CDT_MBN);
+ ddr_init_function = load_ipq_blob(CONFIG_DDR_MBN);
if (!cdt || !ddr_init_function) {
printk(BIOS_ERR, "cdt: %p, ddr_init_function: %p\n",
@@ -76,7 +100,11 @@ int initialize_dram(void)
die("could not find DDR initialization blobs\n");
}
- if (ddr_init_function(cdt) < 0)
+ cdt_header.size = cdt->mbn_total_size;
+ cdt_header.cdt_ptr = (uint8_t *)(cdt + 1);
+
+ sbl_rw_ret_info = ddr_init_function(&cdt_header);
+ if (sbl_rw_ret_info == NULL)
die("Fail to Initialize DDR\n");
/*
@@ -86,14 +114,19 @@ int initialize_dram(void)
printk(BIOS_INFO, "DDR version %.*s initialized\n",
MAX_DDR_VERSION_SIZE, DDR_VERSION());
+ printk(BIOS_INFO, "SDI Entry: 0x%llx\n", sbl_rw_ret_info->sdi_entry);
+ sw_entry = read32(TCSR_RESET_DEBUG_SW_ENTRY) & 0x1;
+ sw_entry |= (sbl_rw_ret_info->sdi_entry & ~0x1);
+ write32(TCSR_RESET_DEBUG_SW_ENTRY, sw_entry);
+ sbl_rw_ret_info->qsee_info->entry_point = (uint32_t)tzbsp;
+
return 0;
}
#else /* __PRE_RAM__ */
-
void start_tzbsp(void)
{
- void *tzbsp = load_ipq_blob("tz.mbn");
+ void *tzbsp = load_ipq_blob(CONFIG_TZ_MBN);
if (!tzbsp)
die("could not find or map TZBSP\n");
@@ -101,55 +134,6 @@ void start_tzbsp(void)
printk(BIOS_INFO, "Starting TZBSP\n");
tz_init_wrapper(0, 0, tzbsp);
-}
-
-/* RPM version is encoded in a 32 bit word at the fixed address */
-#define RPM_VERSION() (*((u32 *)(0x00108008)))
-void start_rpm(void)
-{
- u32 load_addr;
- u32 ready_mask = 1 << 10;
- u32 rpm_version;
-
- struct stopwatch sw;
- if (read32(RPM_SIGNAL_COOKIE) == RPM_FW_MAGIC_NUM) {
- printk(BIOS_INFO, "RPM appears to have already started\n");
- return;
- }
-
- load_addr = (u32) load_ipq_blob("rpm.mbn");
- if (!load_addr)
- die("could not find or map RPM code\n");
-
- printk(BIOS_INFO, "Starting RPM\n");
-
- /* Clear 'ready' indication. */
- /*
- * RPM_INT_ACK is clear-on-write type register,
- * read-modify-write is not recommended.
- */
- write32(RPM_INT_ACK, ready_mask);
-
- /* Set RPM entry address */
- write32(RPM_SIGNAL_ENTRY, load_addr);
- /* Set cookie */
- write32(RPM_SIGNAL_COOKIE, RPM_FW_MAGIC_NUM);
-
- /* Wait for RPM start indication, up to 100ms. */
- stopwatch_init_usecs_expire(&sw, 100000);
- while (!(read32(RPM_INT) & ready_mask))
- if (stopwatch_expired(&sw))
- die("RPM Initialization failed\n");
-
- /* Acknowledge RPM initialization */
- write32(RPM_INT_ACK, ready_mask);
-
- /* Report RPM version, it is encoded in a 32 bit value. */
- rpm_version = RPM_VERSION();
- printk(BIOS_INFO, "Started RPM version %d.%d.%d\n",
- rpm_version >> 24,
- (rpm_version >> 16) & 0xff,
- rpm_version & 0xffff);
}
#endif /* !__PRE_RAM__ */
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
index bfdfb56..0bc8a30 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
@@ -130,6 +130,9 @@ enum {
#define BLSP1_QUP2_BASE ((void *)0x078B7000)
#define BLSP1_QUP3_BASE ((void *)0x078B8000)
+#define TCSR_BOOT_MISC_DETECT ((void *)0x0193D100)
+#define TCSR_RESET_DEBUG_SW_ENTRY ((void *)0x01940000)
+
static inline void *blsp_qup_base(blsp_qup_id_t id)
{
switch (id) {
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