[coreboot-gerrit] Patch set updated for coreboot: soc/qualcomm/ipq40xx: Update DRAM address ranges
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Sat May 7 10:38:47 CEST 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14655
-gerrit
commit 800643c683880e65c76369ad818254530c753348
Author: Varadarajan Narayanan <varada at codeaurora.org>
Date: Mon Sep 7 14:52:47 2015 +0530
soc/qualcomm/ipq40xx: Update DRAM address ranges
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Change-Id: Icc3119b60a255e7f9ceb4f031678ee63370c6235
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 9150c125cb82f8dccb1347d898106703d85a5192
Original-Change-Id: Ic48d3e3f46a7c13a009a5cbed20984bd253eb85b
Original-Signed-off-by: Varadarajan Narayanan <varada at codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333296
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
src/mainboard/google/gale/mmu.c | 17 ++++++++---------
src/mainboard/google/gale/mmu.h | 6 ++++--
src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld | 10 +++++-----
3 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c
index c3b9f0f..65797e7 100644
--- a/src/mainboard/google/gale/mmu.c
+++ b/src/mainboard/google/gale/mmu.c
@@ -14,15 +14,14 @@
#include <symbols.h>
#include "mmu.h"
-/* convenient shorthand (in MB) */
-#define RPM_START ((uintptr_t)_rpm / KiB)
-#define RPM_END ((uintptr_t)_erpm / KiB)
-#define RPM_SIZE (RPM_END - RPM_START)
-#define SRAM_START ((uintptr_t)_sram / KiB)
-#define SRAM_END ((uintptr_t)_esram / KiB)
-#define DRAM_START ((uintptr_t)_dram / MiB)
-#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB)
-#define DRAM_END (DRAM_START + DRAM_SIZE)
+#define WIFI_IMEM_0_START ((uintptr_t)_wifi_imem_0 / KiB)
+#define WIFI_IMEM_0_END ((uintptr_t)_ewifi_imem_0 / KiB)
+#define WIFI_IMEM_1_START ((uintptr_t)_wifi_imem_1 / KiB)
+#define WIFI_IMEM_1_END ((uintptr_t)_ewifi_imem_1 / KiB)
+
+#define DRAM_START ((uintptr_t)_dram / MiB)
+#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB)
+#define DRAM_END (DRAM_START + DRAM_SIZE)
/* DMA memory for drivers */
#define DMA_START ((uintptr_t)_dma_coherent / MiB)
diff --git a/src/mainboard/google/gale/mmu.h b/src/mainboard/google/gale/mmu.h
index 956553d..e3347c8 100644
--- a/src/mainboard/google/gale/mmu.h
+++ b/src/mainboard/google/gale/mmu.h
@@ -12,8 +12,10 @@
#include <types.h>
-extern u8 _rpm[];
-extern u8 _erpm[];
+extern u8 _wifi_imem_0[]; /* Linker script supplied */
+extern u8 _ewifi_imem_0[];
+extern u8 _wifi_imem_1[];
+extern u8 _ewifi_imem_1[];
enum dram_state {
DRAM_INITIALIZED = 0,
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
index 8baf1b0..de8488a 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
@@ -56,9 +56,9 @@ SECTIONS
REGION_END(wifi_imem_1, 0x0A900000)
/* ==^^^== WIFI_IMEM_1_END 0x0A900000 ==^^^== */
- DRAM_START(0x40000000)
- RAMSTAGE(0x40640000, 128K)
- SYMBOL(memlayout_cbmem_top, 0x59F80000)
- POSTRAM_CBFS_CACHE(0x59F80000, 384K)
- DMA_COHERENT(0x5A000000, 2M)
+ DRAM_START(0x80000000)
+ RAMSTAGE(0x80640000, 128K)
+ SYMBOL(memlayout_cbmem_top, 0x89F80000)
+ POSTRAM_CBFS_CACHE(0x89F80000, 384K)
+ DMA_COHERENT(0x8A000000, 2M)
}
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