[coreboot-gerrit] Patch set updated for coreboot: rockchip/spi: Allow SPI buses > 2

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14723

-gerrit

commit 7d7009b24956d5b2a773fe1341fd315cfb68432c
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Thu Apr 28 08:02:14 2016 +0200

    rockchip/spi: Allow SPI buses > 2
    
    If SPI_BASEx is defined (for 2 < x <= 5), allow selecting it.
    Since the bus number translates into an offset into an array, require
    that all earlier buses are defined, too.
    
    Also assert() that the array is properly sized instead of blindly
    exceeding its bounds when called with a too big bus number.
    
    TEST=initializing bus 5 doesn't trap anymore on kevin
    BRANCH=none
    BUG=none
    
    Change-Id: I69f8ebe10854976608197a13d223ee8a555a9545
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c4af2a4ad4d6eea551653ca300ea6d04f1280919
    Original-Change-Id: I27724d64d822ed0ec824a69ed611140bfbe08f5a
    Original-Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Reviewed-on: https://chromium-review.googlesource.com/341034
    Original-Commit-Ready: Vadim Bendebury <vbendeb at chromium.org>
    Original-Tested-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/soc/rockchip/common/spi.c | 33 ++++++++++++++++++++++++++++++---
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c
index 814f0b5..6784f5b 100644
--- a/src/soc/rockchip/common/spi.c
+++ b/src/soc/rockchip/common/spi.c
@@ -35,7 +35,7 @@ struct rockchip_spi_slave {
 #define SPI_SRCCLK_HZ   (99*MHz)
 #define SPI_FIFO_DEPTH	32
 
-static struct rockchip_spi_slave rockchip_spi_slaves[3] = {
+static struct rockchip_spi_slave rockchip_spi_slaves[] = {
 	{
 	 .slave = {
 		   .bus = 0,
@@ -54,7 +54,33 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = {
 		   },
 	 .regs = (void *)SPI2_BASE,
 	},
-
+#ifdef SPI3_BASE
+	{
+	 .slave = {
+		   .bus = 3,
+		   .rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
+		   },
+	 .regs = (void *)SPI3_BASE,
+	},
+#ifdef SPI4_BASE
+	{
+	 .slave = {
+		   .bus = 4,
+		   .rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
+		   },
+	 .regs = (void *)SPI4_BASE,
+	},
+#ifdef SPI5_BASE
+	{
+	 .slave = {
+		   .bus = 5,
+		   .rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
+		   },
+	 .regs = (void *)SPI5_BASE,
+	},
+#endif
+#endif
+#endif
 };
 
 static struct rockchip_spi_slave *to_rockchip_spi(struct spi_slave *slave)
@@ -64,7 +90,7 @@ static struct rockchip_spi_slave *to_rockchip_spi(struct spi_slave *slave)
 
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
 {
-	assert(bus >= 0 && bus < 3);
+	assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves));
 	return &(rockchip_spi_slaves[bus].slave);
 }
 
@@ -97,6 +123,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz)
 
 void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
 {
+	assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves));
 	struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs;
 	unsigned int ctrlr0 = 0;