[coreboot-gerrit] New patch to review for coreboot: rockchip: rk3399: enable pwm

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14714

-gerrit

commit a37d4fcdb4f254c4119eb8bcdbd921398053d7ad
Author: Lin Huang <hl at rock-chips.com>
Date:   Wed Mar 23 19:35:46 2016 +0800

    rockchip: rk3399: enable pwm
    
    Reuse the rockchip common pwm driver.
    
    BRANCH=none
    BUG=chrome-os-partner:51537
    TEST=emerge-kevin coreboot
    
    Change-Id: I1a1ab237f891f06affb74817b5cae1a034a9760e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 37afce0f94435ffef8bdd74b4251430f11ec22f4
    Original-Change-Id: Ia94985f56e424d049fdcc5be86c696577d52a07c
    Original-Signed-off-by: Lin Huang <hl at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/333255
    Original-Commit-Ready: Vadim Bendebury <vbendeb at chromium.org>
    Original-Tested-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/soc/rockchip/rk3399/Makefile.inc             | 1 +
 src/soc/rockchip/rk3399/include/soc/addressmap.h | 1 +
 src/soc/rockchip/rk3399/include/soc/clock.h      | 2 ++
 3 files changed, 4 insertions(+)

diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index bd6200f..773d87f 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -41,6 +41,7 @@ romstage-y += ../common/spi.c
 romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
 romstage-y += clock.c
 romstage-y += mmu_operations.c
+romstage-y += ../common/pwm.c
 romstage-y += timer.c
 romstage-y += romstage.c
 
diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h
index 90d1356..30bb464 100644
--- a/src/soc/rockchip/rk3399/include/soc/addressmap.h
+++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h
@@ -56,6 +56,7 @@
 
 #define TSADC_BASE		0xff260000
 #define SARADC_BASE		0xff100000
+#define RK_PWM_BASE		0xff420000
 
 #define IC_BASES  { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE,		\
 			I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE }
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h
index 4c5a455..ff4edb5 100644
--- a/src/soc/rockchip/rk3399/include/soc/clock.h
+++ b/src/soc/rockchip/rk3399/include/soc/clock.h
@@ -95,6 +95,8 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE;
 #define PERILP1_HCLK_HZ	(99000*KHz)
 #define PERILP1_PCLK_HZ	(49500*KHz)
 
+#define PWM_CLOCK_HZ    PMU_PCLK_HZ
+
 enum apll_l_frequencies {
 	APLL_L_1600_MHZ,
 	APLL_L_600_MHZ,