[coreboot-gerrit] New patch to review for coreboot: google/gru: enable uart2 if configured

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14709

-gerrit

commit 7770a38a443d1bc89d95aaa51448f9537ffc9d7f
Author: Shunqian Zheng <zhengsq at rock-chips.com>
Date:   Wed Apr 13 22:30:07 2016 +0800

    google/gru: enable uart2 if configured
    
    This patch select gpio pins for UART2 which is the default
    debug port of rk3399.
    
    Please refer to TRM V0.3 Part1 Page 325,395 for GRF details.
    
    BRANCH=none
    BUG=chrome-os-partner:51537
    TEST=check logs from console manually
    
    Change-Id: I91eeadd543e7e895c3972d8dd7a2195c9d78968b
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 0c51955e18d4ff9cd3208697666af4fa77046e0f
    Original-Change-Id: I960178628f4020a59d100f2f0b2a6be487892549
    Original-Signed-off-by: hunag lin <hl at rock-chips.com>
    Original-Signed-off-by: Shunqian Zheng <zhengsq at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/338945
    Original-Commit-Ready: Vadim Bendebury <vbendeb at chromium.org>
    Original-Tested-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/mainboard/google/gru/bootblock.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index bdc75dd..1a99e84 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -14,10 +14,23 @@
  *
  */
 
+#include <arch/io.h>
 #include <bootblock_common.h>
+#include <soc/grf.h>
+#include <console/console.h>
 
 void bootblock_mainboard_early_init(void)
 {
+	if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
+		_Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE,
+			       "CONSOLE_SERIAL_UART should be UART2");
+
+		/* iomux: select gpio4c[4:3] as uart2 dbg port */
+		write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C);
+
+		/* grf soc_con7[11:10] use for uart2 select */
+		write32(&rk3399_grf->soc_con7, UART2C_SEL);
+	}
 }
 
 void bootblock_mainboard_init(void)