[coreboot-gerrit] New patch to review for coreboot: rockchip: rk3399: add functions to configure ddrc freq

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14707

-gerrit

commit df1a7054d2fde84bc671a4cbbd4596026ac6872e
Author: Shunqian Zheng <zhengsq at rock-chips.com>
Date:   Thu Apr 21 23:53:08 2016 +0800

    rockchip: rk3399: add functions to configure ddrc freq
    
    This patch list four frequencies for ddr controller,
    200MHz, 300MHz, 666MHz and 800MHz and configure
    each freq by setting the DPLL dividers.
    
    By default, the clk_ddrc is from DPLL and equals to DPLL,
    so here we only need to set the DPLL clock.
    
    BRANCH=none
    BUG=chrome-os-partner:51537
    TEST=emerge-kevin coreboot
    
    Change-Id: Ifabe85b5dc95e3c8e3e9cbf946e12e8b06b881cf
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 18ec4f7d8738472fbadd60fa3c8f810f5347ffa2
    Original-Change-Id: I448057542c3885068ddffa5b37d0341ee3ec04b1
    Original-Signed-off-by: Shunqian Zheng <zhengsq at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/340184
    Original-Commit-Ready: Vadim Bendebury <vbendeb at chromium.org>
    Original-Tested-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/soc/rockchip/rk3399/clock.c             | 41 +++++++++++++++++++++++++++++
 src/soc/rockchip/rk3399/include/soc/clock.h |  1 +
 2 files changed, 42 insertions(+)

diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 7053a37..c2a1691 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -137,6 +137,16 @@ enum {
 	HCLK_PERILP1_PLL_SEL_GPLL	= 1,
 	HCLK_PERILP1_DIV_CON_MASK	= 0x1f,
 	HCLK_PERILP1_DIV_CON_SHIFT	= 0,
+
+	/* CRU_SOFTRST_CON4 */
+	RESETN_DDR0_REQ_MASK		= 1,
+	RESETN_DDR0_REQ_SHIFT		= 8,
+	RESETN_DDRPHY0_REQ_MASK		= 1,
+	RESETN_DDRPHY0_REQ_SHIFT	= 9,
+	RESETN_DDR1_REQ_MASK		= 1,
+	RESETN_DDR1_REQ_SHIFT		= 12,
+	RESETN_DDRPHY1_REQ_MASK		= 1,
+	RESETN_DDRPHY1_REQ_SHIFT	= 13,
 };
 
 #define VCO_MAX_KHZ	(3200 * (MHz / KHz))
@@ -350,6 +360,37 @@ void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq)
 			      atclk_div << ATCLK_CORE_L_DIV_SHIFT));
 }
 
+void rkclk_configure_ddr(unsigned int hz)
+{
+	struct pll_div dpll_cfg;
+
+	/* IC ECO bug, need to set this register */
+	write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xc000c000);
+
+	/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
+	switch (hz) {
+	case 200*MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
+		break;
+	case 300*MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
+		break;
+	case 666*MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
+		break;
+	case 800*MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
+		break;
+	default:
+		die("Unsupported SDRAM frequency, add to clock.c!");
+	}
+	rkclk_set_pll(&cru_ptr->dpll_con[0], &dpll_cfg);
+}
+
 void rkclk_configure_spi(unsigned int bus, unsigned int hz)
 {
 }
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h
index 9b54799..cb4d325 100644
--- a/src/soc/rockchip/rk3399/include/soc/clock.h
+++ b/src/soc/rockchip/rk3399/include/soc/clock.h
@@ -102,5 +102,6 @@ enum apll_l_frequencies {
 
 void rkclk_init(void);
 void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq);
+void rkclk_configure_ddr(unsigned int hz);
 void rkclk_configure_spi(unsigned int bus, unsigned int hz);
 #endif	/* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */