[coreboot-gerrit] Patch set updated for coreboot: google/oak: Add derivative board Elm
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Sat May 7 08:08:00 CEST 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14691
-gerrit
commit e7a90a3fa03f881cdfa97fad3e51950d0cc3f18e
Author: Julius Werner <jwerner at chromium.org>
Date: Mon Mar 14 20:12:18 2016 -0700
google/oak: Add derivative board Elm
This patch adds a new mainboard Google/Elm as a derivative of
Google/Oak, using the same code sharing technique for derivative boards
that was pioneered with Google/Veyron*. For now, there are no
firmware-relevant fundamental differences between the two boards.
In addition, introduce a board-specific Kconfig for the "board ID
adjustment" to represent the fact that the Elm board ID space mirrors
the Oak board ID space with an offset of 6, meaning Elm rev0 is
equivalent to Oak rev6, and future board changes will be made on both
boards to maintain this stride (at least virtually... not all of those
revisions will necessarily get built). This should make it much easier
to keep the code that handles revision differences somewhat clean.
(That's the theory, anyway... whether it will work out remains to be
seen.)
BRANCH=None
BUG=None
TEST=Booted Elm image with hardcoded board ID 0 on Oak rev6.
Change-Id: If540aea862b746cf4986a74482ae1764c104fb73
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 53cd85c94945ab0bf14cb88a98e66723fc4483de
Original-Change-Id: Ib05fc81dc4f4308d99e34fce74c6db8b323785da
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332276
Original-Commit-Ready: Yidi Lin <yidi.lin at mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin at mediatek.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/oak/Kconfig | 18 ++++++++++++++++--
src/mainboard/google/oak/Kconfig.name | 5 +++++
src/mainboard/google/oak/bootblock.c | 4 ++--
src/mainboard/google/oak/chromeos.c | 2 +-
src/mainboard/google/oak/mainboard.c | 30 ++++++++++++++++++------------
src/mainboard/google/oak/romstage.c | 2 +-
6 files changed, 43 insertions(+), 18 deletions(-)
diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig
index 79d43d4..e8624d2 100644
--- a/src/mainboard/google/oak/Kconfig
+++ b/src/mainboard/google/oak/Kconfig
@@ -13,7 +13,10 @@
## GNU General Public License for more details.
##
-if BOARD_GOOGLE_OAK
+config BOARD_GOOGLE_OAK_COMMON
+ def_bool n
+
+if BOARD_GOOGLE_OAK_COMMON
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -41,7 +44,11 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
string
- default "oak"
+ default "Oak"
+
+config MAINBOARD_VENDOR
+ string
+ default "Google"
config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
@@ -71,4 +78,11 @@ config GBB_HWID
string
depends on CHROMEOS
default "OAK TEST 6858"
+
+# All Oak-derivatives count their board IDs as 0 being equivalent to Oak rev6.
+config BOARD_ID_ADJUSTMENT
+ int
+ default 0 if BOARD_GOOGLE_OAK
+ default 6
+
endif # BOARD_GOOGLE_OAK
diff --git a/src/mainboard/google/oak/Kconfig.name b/src/mainboard/google/oak/Kconfig.name
index 49e27d7..ba85ad8 100644
--- a/src/mainboard/google/oak/Kconfig.name
+++ b/src/mainboard/google/oak/Kconfig.name
@@ -1,2 +1,7 @@
config BOARD_GOOGLE_OAK
bool "Oak"
+ select BOARD_GOOGLE_OAK_COMMON
+
+config BOARD_GOOGLE_ELM
+ bool "Elm"
+ select BOARD_GOOGLE_OAK_COMMON
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index 2c13b14..325889c 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -81,7 +81,7 @@ void bootblock_mainboard_init(void)
nor_set_gpio_pinmux();
/* SPI_LEVEL_ENABLE: Enable 1.8V to 3.3V level shifter for EC SPI bus */
- if (board_id() > 4)
+ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4)
gpio_output(PAD_SRCLKENAI2, 1);
/* Init i2c bus 2 Timing register for TPM */
@@ -91,6 +91,6 @@ void bootblock_mainboard_init(void)
setup_chromeos_gpios();
- if (board_id() < 4)
+ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 4)
mt6391_enable_reset_when_ap_resets();
}
diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c
index ea6d21f..0265c7a 100644
--- a/src/mainboard/google/oak/chromeos.c
+++ b/src/mainboard/google/oak/chromeos.c
@@ -31,7 +31,7 @@ void setup_chromeos_gpios(void)
gpio_input_pullup(EC_IRQ);
gpio_input_pullup(LID);
gpio_input_pullup(POWER_BUTTON);
- if (board_id() < 5)
+ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5)
gpio_output(EC_SUSPEND_L, 1);
}
diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c
index 5001a9a..7906593 100644
--- a/src/mainboard/google/oak/mainboard.c
+++ b/src/mainboard/google/oak/mainboard.c
@@ -47,7 +47,7 @@ static void configure_ext_buck(void)
{
mtk_i2c_bus_init(EXT_BUCK_I2C_BUS);
- switch (board_id()) {
+ switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
case 3:
case 4:
/* rev-3 and rev-4 use mt6311 as external buck */
@@ -78,7 +78,7 @@ static void configure_audio(void)
mt6391_configure_ldo(LDO_VCAMA, LDO_1P8);
/* reset ALC5676 */
- if (board_id() < 5)
+ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5)
gpio_output(PAD_LCM_RST, 1);
/* SoC I2S */
@@ -87,7 +87,7 @@ static void configure_audio(void)
gpio_set_mode(PAD_I2S0_MCK, PAD_I2S0_MCK_FUNC_I2S1_MCK);
gpio_set_mode(PAD_I2S0_DATA0, PAD_I2S0_DATA0_FUNC_I2S1_DO_1);
gpio_set_mode(PAD_I2S0_DATA1, PAD_I2S0_DATA1_FUNC_I2S2_DI_2);
- if (board_id() >= 5)
+ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT >= 5)
gpio_set_mode(PAD_UCTS0, PAD_UCTS0_FUNC_I2S2_DI_1);
/* codec ext MCLK ON */
@@ -105,7 +105,7 @@ static void configure_usb(void)
{
setup_usb_host();
- if (board_id() > 3) {
+ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 3) {
/* Enable current limit */
gpio_output(PAD_CM2MCLK, 1);
/* Configure USB OC pins*/
@@ -114,7 +114,7 @@ static void configure_usb(void)
gpio_input_pullup(PAD_PCM_SYNC);
}
- if (board_id() > 4) {
+ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4) {
/* USB 2.0 type A port over current interrupt pin(low active) */
gpio_input_pullup(PAD_UCTS2);
/* USB 2.0 type A port BC1.2 STATUS(low active) */
@@ -125,7 +125,7 @@ static void configure_usb(void)
static void configure_usb_hub(void)
{
/* set usb hub reset pin (low active) to high */
- if (board_id() > 4)
+ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4)
gpio_output(PAD_UTXD3, 1);
}
@@ -133,7 +133,7 @@ static void configure_usb_hub(void)
static void configure_backlight(void)
{
/* Configure PANEL_LCD_POWER_EN */
- switch (board_id()) {
+ switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
case 1:
case 2:
break;
@@ -156,7 +156,7 @@ static void configure_display(void)
{
mtcmos_display_power_on();
- switch (board_id()) {
+ switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
case 0:
/* board from Rev0, Rev1 */
/* vgp2 set to 1.8V for it6151 */
@@ -182,11 +182,17 @@ static void configure_display(void)
mt6391_configure_ldo(LDO_VGP2, LDO_3P3);
gpio_output(PAD_URTS0, 0); /* PS8640_SYSRSTN */
/* PS8640_1V2_ENABLE */
- gpio_output(board_id() == 4 ? PAD_SRCLKENAI2 : PAD_URTS2, 1);
+ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT == 4)
+ gpio_output(PAD_SRCLKENAI2, 1);
+ else
+ gpio_output(PAD_URTS2, 1);
/* delay 2ms for vgp2 and PS8640_1V2_ENABLE stable */
mdelay(2);
/* PS8640_PDN */
- gpio_output(board_id() > 4 ? PAD_LCM_RST : PAD_UCTS0, 1);
+ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4)
+ gpio_output(PAD_LCM_RST, 1);
+ else
+ gpio_output(PAD_UCTS0, 1);
gpio_output(PAD_PCM_CLK, 1); /* PS8640_MODE_CONF */
gpio_output(PAD_URTS0, 1); /* PS8640_SYSRSTN */
/* for level shift(1.8V to 3.3V) on */
@@ -200,7 +206,7 @@ static void display_startup(void)
u8 i2c_bus;
int ret;
- switch (board_id()) {
+ switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
case 0:
case 1:
i2c_bus = 3;
@@ -240,7 +246,7 @@ static void mainboard_init(device_t dev)
/* TP_SHIFT_EN: Enables the level shifter for I2C bus 4 (TPAD), which
* also contains the PS8640 eDP brige and the USB hub.
*/
- if (board_id() < 5)
+ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5)
mt6391_gpio_output(MT6391_KP_ROW2, 1);
/* Config SD card detection pin */
diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c
index 3d018a0..a92e4fb 100644
--- a/src/mainboard/google/oak/romstage.c
+++ b/src/mainboard/google/oak/romstage.c
@@ -59,7 +59,7 @@ void main(void)
;
/* Set to maximum frequency */
- if (board_id() < 5)
+ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5)
mt_pll_raise_ca53_freq(1600 * MHz);
else
mt_pll_raise_ca53_freq(1700 * MHz);
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