[coreboot-gerrit] New patch to review for coreboot: soc/qualcomm/ipq40xx: Add function to reset TPM

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14676

-gerrit

commit 90e2620ffb4926b47c94b95a7daa29b37940a27d
Author: Varadarajan Narayanan <varada at codeaurora.org>
Date:   Wed Nov 25 14:16:09 2015 +0530

    soc/qualcomm/ipq40xx: Add function to reset TPM
    
    BUG=chrome-os-partner:49249
    TEST=Able to read TPM registers
    BRANCH=none
    
    Change-Id: I2f624b974001d439f3266203f4fc204f51f933e6
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 9df3e9dfe61382143394a58a3a927c05a875b377
    Original-Change-Id: I38732acc4418c94b88a430ba697db4e3b145c341
    Original-Signed-off-by: Varadarajan Narayanan <varada at codeaurora.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/333317
    Original-Commit-Ready: David Hendricks <dhendrix at chromium.org>
    Original-Tested-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
 src/mainboard/google/gale/mainboard.c | 35 ++++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c
index 075c0ba..78d7c5b 100644
--- a/src/mainboard/google/gale/mainboard.c
+++ b/src/mainboard/google/gale/mainboard.c
@@ -40,6 +40,39 @@ static void setup_usb(void)
 	setup_usb_host1();
 }
 
+#define TPM_RESET_GPIO		19
+static void ipq_setup_tpm(void)
+{
+#ifdef CONFIG_I2C_TPM
+	gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO,
+			     GPIO_PULL_UP, GPIO_6MA, 1);
+	gpio_set(TPM_RESET_GPIO, 0);
+	udelay(100);
+	gpio_set(TPM_RESET_GPIO, 1);
+
+	/*
+	 * ----- Per the SLB 9615XQ1.2 spec -----
+	 *
+	 * 4.7.1 Reset Timing
+	 *
+	 * The TPM_ACCESS_x.tpmEstablishment bit has the correct value
+	 * and the TPM_ACCESS_x.tpmRegValidSts bit is typically set
+	 * within 8ms after RESET# is deasserted.
+	 *
+	 * The TPM is ready to receive a command after less than 30 ms.
+	 *
+	 * --------------------------------------
+	 *
+	 * I'm assuming this means "wait for 30ms"
+	 *
+	 * If we don't wait here, subsequent QUP I2C accesses
+	 * to the TPM either fail or timeout.
+	 */
+	mdelay(30);
+
+#endif /* CONFIG_I2C_TPM */
+}
+
 static void mainboard_init(device_t dev)
 {
 	/* disable mmu and d-cache before setting up secure world.*/
@@ -48,7 +81,7 @@ static void mainboard_init(device_t dev)
 	/* Setup mmu and d-cache again as non secure entries. */
 	setup_mmu(DRAM_INITIALIZED);
 	setup_usb();
-	setup_tpm();
+	ipq_setup_tpm();
 
 #if IS_ENABLED(CONFIG_CHROMEOS)
 	/* Copy WIFI calibration data into CBMEM. */