[coreboot-gerrit] New patch to review for coreboot: soc/qualcomm/ipq40xx: Enable timer
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Fri May 6 23:28:22 CEST 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14667
-gerrit
commit be16315fd7a5f8dfb0fd42d8c2420973621e1fed
Author: Varadarajan Narayanan <varada at codeaurora.org>
Date: Thu Mar 3 13:30:07 2016 +0530
soc/qualcomm/ipq40xx: Enable timer
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Change-Id: I5e31d036ee7ddcf72ed9739cef1f7f7d0ca6c427
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 35c0e6046899dc1af03736ae9fa77f9eeec7f668
Original-Change-Id: I681e92fa673c1d3aee2974a7bba5074e2bfd6e02
Original-Signed-off-by: Varadarajan Narayanan <varada at codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333297
Original-Commit-Ready: David Hendricks <dhendrix at chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
src/soc/qualcomm/ipq40xx/include/soc/iomap.h | 54 +++++++-----------------
src/soc/qualcomm/ipq40xx/timer.c | 63 +++++++++++-----------------
2 files changed, 40 insertions(+), 77 deletions(-)
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
index 543356d..def8058 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
@@ -49,37 +49,21 @@
#define clrsetbits_le32_i(addr, clear, set) \
clrsetbits_le32(((void *)(addr)), (clear), (set))
-#define MSM_CLK_CTL_BASE ((void *)0x00900000)
-
-#define MSM_TMR_BASE ((void *)0x0200A000)
-#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04)
-#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
-
-#define GPT_REG(off) (MSM_GPT_BASE + (off))
-#define DGT_REG(off) (MSM_DGT_BASE + (off))
-
-#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040)
-#define APCS_WDT0_RST (MSM_TMR_BASE + 0x0038)
-#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C)
-#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C)
-
-#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820)
-
-#define GPT_MATCH_VAL GPT_REG(0x0000)
-#define GPT_COUNT_VAL GPT_REG(0x0004)
-#define GPT_ENABLE GPT_REG(0x0008)
-#define GPT_CLEAR GPT_REG(0x000C)
+/*
+ * FIXME:
+ * Temporary define to escape compiler errors
+ * Should be removed once things are cleaned up
+ */
+#define MSM_CLK_CTL_BASE ((void *)0x00900000)
-#define GPT1_MATCH_VAL GPT_REG(0x00010)
-#define GPT1_COUNT_VAL GPT_REG(0x00014)
-#define GPT1_ENABLE GPT_REG(0x00018)
-#define GPT1_CLEAR GPT_REG(0x0001C)
+#define GCNT_GLOBAL_CTRL_BASE ((void *)0x004a0000u)
+#define GCNT_CNTCR (GCNT_GLOBAL_CTRL_BASE + 0x1000)
+#define GCNT_GLB_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x1008)
+#define GCNT_GLB_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x100c)
+#define GCNT_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x2000)
+#define GCNT_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x2004)
-#define DGT_MATCH_VAL DGT_REG(0x0000)
-#define DGT_COUNT_VAL DGT_REG(0x0004)
-#define DGT_ENABLE DGT_REG(0x0008)
-#define DGT_CLEAR DGT_REG(0x000C)
-#define DGT_CLK_CTL DGT_REG(0x0010)
+#define GCNT_PSHOLD ((void *)0x004AB000u)
/* RPM interface constants */
#define RPM_INT ((void *)0x63020)
@@ -88,8 +72,8 @@
#define RPM_SIGNAL_ENTRY ((void *)0x47C24)
#define RPM_FW_MAGIC_NUM 0x4D505242
-#define TLMM_BASE_ADDR ((void *)0x00800000)
-#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
+#define TLMM_BASE_ADDR ((void *)0x01000000)
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 * (x))
#define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4)
/* Yes, this is not a typo... host2 is actually mapped before host1. */
@@ -100,16 +84,8 @@
#define USB_HOST1_DWC3_BASE 0x1100C100
#define USB_HOST1_PHY_BASE 0x110F8800
-#define GSBI_4 4
#define UART1_DM_BASE 0x12450000
-#define UART_GSBI1_BASE 0x12440000
#define UART2_DM_BASE 0x12490000
-#define UART_GSBI2_BASE 0x12480000
-#define UART4_DM_BASE 0x16340000
-#define UART_GSBI4_BASE 0x16300000
-
-#define UART2_DM_BASE 0x12490000
-#define UART_GSBI2_BASE 0x12480000
#define GSBI1_BASE ((void *)0x12440000)
#define GSBI2_BASE ((void *)0x12480000)
diff --git a/src/soc/qualcomm/ipq40xx/timer.c b/src/soc/qualcomm/ipq40xx/timer.c
index 7b8c1f0..d5650ec 100644
--- a/src/soc/qualcomm/ipq40xx/timer.c
+++ b/src/soc/qualcomm/ipq40xx/timer.c
@@ -32,20 +32,10 @@
#include <soc/ipq_timer.h>
#include <timer.h>
-/*
- * DGT runs at 25 MHz / 4, or 6.25 ticks per microsecond
- */
-#define DGT_MHZ_NUM 25
-#define DGT_MHZ_DEN 4
-
-#define TIMER_TICKS(us) ((DGT_MHZ_NUM*(us) + (DGT_MHZ_DEN - 1)) / DGT_MHZ_DEN)
-#define TIMER_USECS(ticks) (DGT_MHZ_DEN*(ticks) / DGT_MHZ_NUM)
+#define GCNT_FREQ_MHZ 48
-/* Clock divider values for the timer. */
-#define DGT_CLK_DIV_1 0
-#define DGT_CLK_DIV_2 1
-#define DGT_CLK_DIV_3 2
-#define DGT_CLK_DIV_4 3
+#define TIMER_TICKS(us) (GCNT_FREQ_MHZ * (us))
+#define TIMER_USECS(ticks) ((ticks) / GCNT_FREQ_MHZ)
/**
* init_timer - initialize timer
@@ -53,18 +43,26 @@
void init_timer(void)
{
/* disable timer */
- writel_i(0, DGT_ENABLE);
+ write32(GCNT_CNTCR, 0);
- /* DGT uses TCXO source which is 25MHz.
- * The timer should run at 1/4th the frequency of TCXO
- * according to clock plan.
- * Set clock divider to 4.
- */
- writel_i(DGT_CLK_DIV_4, DGT_CLK_CTL);
+ /* Reset the counters to zero */
+ write32(GCNT_GLB_CNTCV_LO, 0);
+ write32(GCNT_GLB_CNTCV_HI, 0);
/* Enable timer */
- writel_i(0, DGT_CLEAR);
- writel_i(DGT_ENABLE_EN, DGT_ENABLE);
+ write32(GCNT_CNTCR, 1);
+}
+
+static inline uint64_t read_gcnt_val(void)
+{
+ uint32_t hi, lo;
+
+ do {
+ hi = read32(GCNT_CNTCV_HI);
+ lo = read32(GCNT_CNTCV_LO);
+ } while (hi != read32(GCNT_CNTCV_HI));
+
+ return ((((uint64_t)hi) << 32) | lo);
}
/**
@@ -73,26 +71,15 @@ void init_timer(void)
*/
void udelay(unsigned usec)
{
- uint32_t now;
- uint32_t last;
- uint32_t ticks;
- uint32_t curr_ticks = 0;
-
- /* Calculate number of ticks required. */
- ticks = TIMER_TICKS(usec);
+ uint64_t expire;
- /* Obtain the current timer value. */
- last = readl_i(DGT_COUNT_VAL);
+ expire = read_gcnt_val() + TIMER_TICKS(usec);
- /* Loop until the right number of ticks. */
- while (curr_ticks < ticks) {
- now = readl_i(DGT_COUNT_VAL);
- curr_ticks += now - last;
- last = now;
- }
+ while (expire >= read_gcnt_val())
+ ;
}
void timer_monotonic_get(struct mono_time *mt)
{
- mono_time_set_usecs(mt, TIMER_USECS(readl_i(DGT_COUNT_VAL)));
+ mono_time_set_usecs(mt, TIMER_USECS(read_gcnt_val()));
}
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