[coreboot-gerrit] New patch to review for coreboot: soc/apollolake: Handle non-standard ACPI BAR in PMC device

[Alexandru Gagniuc (alexandrux.gagniuc@intel.com)]

Alexandru Gagniuc (alexandrux.gagniuc at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14634

-gerrit

commit 703c6ef8192527ef79769e91b0381e4aa04c6f41
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date:   Wed Apr 6 10:49:55 2016 -0700

    soc/apollolake: Handle non-standard ACPI BAR in PMC device
    
    The ACPI BAR (BAR2 - offset 0x20) is not PCI compliant. That means
    that probing may not work. In that case, a resource still needs to be
    created for the BAR.
    
    BONUS: We now avoid the need to declare the MMIO resources as fixed.
    
    Change-Id: I52fd2d2718ac8013067aaa450c5eb31e00738ab9
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/soc/intel/apollolake/pmc.c | 47 +++++++++++++++++++++---------------------
 1 file changed, 24 insertions(+), 23 deletions(-)

diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c
index 0251e7c..7cb1c87 100644
--- a/src/soc/intel/apollolake/pmc.c
+++ b/src/soc/intel/apollolake/pmc.c
@@ -1,7 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,39 +15,39 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
-#include <cpu/cpu.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <soc/iomap.h>
 #include <soc/pci_ids.h>
 
-static void pmc_init(device_t dev)
-{
-	printk(BIOS_SPEW, "%s/%s ( %s )\n",
-		__FILE__, __func__, dev_name(dev));
-}
-
-static void pmc_read_resources(device_t dev)
+/*
+ * The ACPI IO BAR (offset 0x20) is not PCI compliant. In the event that probing
+ * the BAR fails, we still need to create a resource for it. The BAR is also
+ * reprogrammed, as the probing may destructively change the base address.
+ */
+static void read_resources(device_t dev)
 {
 	struct resource *res;
-
-	mmio_resource(dev, PCI_BASE_ADDRESS_0, PMC_BAR0/KiB, 1);
-	mmio_resource(dev, PCI_BASE_ADDRESS_2, PMC_BAR1/KiB, 2);
-
-	res = new_resource(dev, PCI_BASE_ADDRESS_4);
-	res->base = ACPI_PMIO_BASE;
-	res->size = KiB;
-	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	pci_dev_read_resources(dev);
+
+	res = probe_resource(dev, PCI_BASE_ADDRESS_4);
+	if (!res) {
+		res = new_resource(dev, PCI_BASE_ADDRESS_4);
+		res->base = ACPI_PMIO_BASE;
+		res->size = 0x100;
+		res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED |
+			     IORESOURCE_FIXED;
+	}
+
+	/* The ACPI BAR is not PCI-compliant. Re-program it after probing. */
+	pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
 }
 
 static const struct device_operations device_ops = {
-	.read_resources		= pmc_read_resources,
-	.set_resources		= DEVICE_NOOP,
-	.enable_resources	= DEVICE_NOOP,
-	.init			= pmc_init,
-	.enable			= DEVICE_NOOP,
+	.read_resources		= read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
 };
 
 static const struct pci_driver pmc __pci_driver = {