[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Split smihandler code into common and SOC specific
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Thu May 5 03:08:20 CEST 2016
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14615
-gerrit
commit 1157c402c3dbb424ceacbbb01b5b6ad5980bf223
Author: Hannah Williams <hannah.williams at intel.com>
Date: Wed May 4 18:15:49 2016 -0700
soc/apollolake: Split smihandler code into common and SOC specific
Change-Id: I0aefb6dbb2b1cac5961f9e43f4752b5929235df3
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
src/soc/intel/apollolake/Kconfig | 1 +
src/soc/intel/apollolake/smihandler.c | 172 +++++++++++++++++++++
src/soc/intel/common/Kconfig | 4 +
src/soc/intel/common/Makefile.inc | 2 +
src/soc/intel/common/smi.h | 27 ++++
src/soc/intel/common/smihandler.c | 280 ++++++++++++++++++++++++++++++++++
6 files changed, 486 insertions(+)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 7cd548b..20602fa 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS
select REG_SCRIPT
select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
select SOC_INTEL_COMMON
+ select SOC_INTEL_COMMON_SMI
select SPI_FLASH
select UDELAY_TSC
select TSC_CONSTANT_RATE
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c
new file mode 100644
index 0000000..a368de3
--- /dev/null
+++ b/src/soc/intel/apollolake/smihandler.c
@@ -0,0 +1,172 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <device/pci_def.h>
+#include <elog.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/intel/common/smi.h>
+#include <spi-generic.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+static int smm_initialized = 0;
+
+/*
+ * Look for Synchronous IO SMI and use save state from that
+ * core in case we are not running on the same core that
+ * initiated the IO transaction.
+ */
+static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
+{
+ em64t100_smm_state_save_area_t *state;
+ int node;
+
+ /* Check all nodes looking for the one that issued the IO */
+ for (node = 0; node < CONFIG_MAX_CPUS; node++) {
+ state = smm_get_save_state(node);
+
+ /* Check for Synchronous IO (bit0==1) */
+ if (!(state->io_misc_info & (1 << 0)))
+ continue;
+
+ /* Make sure it was a write (bit4==0) */
+ if (state->io_misc_info & (1 << 4))
+ continue;
+
+ /* Check for APMC IO port */
+ if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
+ continue;
+
+ /* Check AX against the requested command */
+ if ((state->rax & 0xff) != cmd)
+ continue;
+
+ return state;
+ }
+
+ return NULL;
+}
+
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
+void smi_gsmi_get_command(uint8_t *sub_command, u32 **param, u32 **ret)
+{
+ em64t100_smm_state_save_area_t *io_smi =
+ smi_apmc_find_state_save(ELOG_GSMI_APM_CNT);
+
+ if (!io_smi)
+ return;
+
+ /* Command and return value in EAX */
+ *ret = (u32 *)&io_smi->rax;
+ *sub_command = (uint8_t)(**ret >> 8);
+
+ /* Parameter buffer in EBX */
+ *param = (u32 *)&io_smi->rbx;
+
+}
+#endif
+
+
+void smi_update_gnvs(struct global_nvs_t **gnvs)
+{
+ em64t100_smm_state_save_area_t *state;
+ if (smm_initialized) {
+ printk(BIOS_DEBUG,
+ "SMI#: SMM structures already initialized!\n");
+ return;
+ }
+ state = smi_apmc_find_state_save(APM_CNT_GNVS_UPDATE);
+ if (state) {
+ /* EBX in the state save contains the GNVS pointer */
+ *gnvs = (struct global_nvs_t *)((uint32_t)state->rbx);
+ smm_initialized = 1;
+ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
+ }
+ return;
+}
+
+
+
+typedef void (*smi_handler_t)(void);
+
+static const smi_handler_t southbridge_smi[32] = {
+ NULL, /* [0] reserved */
+ NULL, /* [1] reserved */
+ NULL, /* [2] BIOS_STS */
+ NULL, /* [3] LEGACY_USB_STS */
+ southbridge_smi_sleep, /* [4] SLP_SMI_STS */
+ southbridge_smi_apmc, /* [5] APM_STS */
+ NULL, /* [6] SWSMI_TMR_STS */
+ NULL, /* [7] reserved */
+ southbridge_smi_pm1, /* [8] PM1_STS */
+ southbridge_smi_gpe0, /* [9] GPE0_STS */
+ NULL, /* [10] reserved */
+ NULL, /* [11] reserved */
+ NULL, /* [12] reserved */
+ southbridge_smi_tco, /* [13] TCO_STS */
+ southbridge_smi_periodic, /* [14] PERIODIC_STS */
+ NULL, /* [15] SERIRQ_SMI_STS */
+ NULL, /* [16] SMBUS_SMI_STS */
+ NULL, /* [17] LEGACY_USB2_STS */
+ NULL, /* [18] INTEL_USB2_STS */
+ NULL, /* [19] reserved */
+ NULL, /* [20] PCI_EXP_SMI_STS */
+ NULL, /* [21] reserved */
+ NULL, /* [22] reserved */
+ NULL, /* [23] reserved */
+ NULL, /* [24] reserved */
+ NULL, /* [25] reserved */
+ NULL, /* [26] SPI_STS */
+ NULL, /* [27] reserved */
+ NULL, /* [28] PUNIT */
+ NULL, /* [29] GUNIT */
+ NULL, /* [30] reserved */
+ NULL /* [31] reserved */
+};
+
+void southbridge_smi_handler(void)
+{
+ int i;
+ uint32_t smi_sts;
+
+ /*
+ * We need to clear the SMI status registers, or we won't see what's
+ * happening in the following calls.
+ */
+ smi_sts = clear_smi_status();
+
+ /* Call SMI sub handler for each of the status bits */
+ for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
+ if (!(smi_sts & (1 << i)))
+ continue;
+
+ if (southbridge_smi[i] != NULL) {
+ southbridge_smi[i]();
+ } else {
+ printk(BIOS_DEBUG,
+ "SMI_STS[%d] occurred, but no "
+ "handler available.\n", i);
+ }
+ }
+}
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 8b68aad..a4081ce 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -59,4 +59,8 @@ config MMA_BLOBS_PATH
depends on MMA
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/mma"
+config SOC_INTEL_COMMON_SMI
+ bool
+ default n
+
endif # SOC_INTEL_COMMON
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index a7218b7..588a0a8 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -15,6 +15,8 @@ ramstage-y += util.c
ramstage-$(CONFIG_MMA) += mma.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c
+smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c
+
# Create and add the MRC cache to the cbfs image
ifneq ($(CONFIG_CHROMEOS),y)
$(obj)/mrc.cache: $(obj)/config.h
diff --git a/src/soc/intel/common/smi.h b/src/soc/intel/common/smi.h
new file mode 100644
index 0000000..64367b7
--- /dev/null
+++ b/src/soc/intel/common/smi.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _INTEL_COMMON_SMI_H_
+#define _INTEL_COMMON_SMI_H_
+
+void smi_update_gnvs(struct global_nvs_t **gnvs);
+void southbridge_smi_sleep(void);
+void southbridge_smi_apmc(void);
+void southbridge_smi_pm1(void);
+void southbridge_smi_gpe0(void);
+void southbridge_smi_tco(void);
+void southbridge_smi_periodic(void);
+
+#endif
diff --git a/src/soc/intel/common/smihandler.c b/src/soc/intel/common/smihandler.c
new file mode 100644
index 0000000..44e4f51
--- /dev/null
+++ b/src/soc/intel/common/smihandler.c
@@ -0,0 +1,280 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <device/pci_def.h>
+#include <elog.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <spi-generic.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "smi.h"
+
+/* GNVS needs to be set by coreboot initiating a software SMI. */
+static struct global_nvs_t *gnvs;
+
+void southbridge_smi_set_eos(void)
+{
+ enable_smi(EOS);
+}
+
+struct global_nvs_t *smm_get_gnvs(void)
+{
+ return gnvs;
+}
+
+static void busmaster_disable_on_bus(int bus)
+{
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
+}
+
+
+void southbridge_smi_sleep(void)
+{
+ uint32_t reg32;
+ uint8_t slp_typ;
+
+ /* First, disable further SMIs */
+ disable_smi(SLP_SMI_EN);
+
+ /* Figure out SLP_TYP */
+ reg32 = inl(ACPI_PMIO_BASE + PM1_CNT);
+ printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
+ slp_typ = (reg32 >> 10) & 7;
+
+ /* Do any mainboard sleep handling */
+ mainboard_smi_sleep(slp_typ-2);
+
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
+ /* Log S3, S4, and S5 entry */
+ if (slp_typ >= 5)
+ elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
+#endif
+ /* Clear pending GPE events */
+ clear_gpe_status();
+
+ /* Next, do the deed. */
+
+ switch (slp_typ) {
+ case SLP_TYP_S0:
+ printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
+ break;
+ case SLP_TYP_S3:
+ printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
+
+ /* Invalidate the cache before going to S3 */
+ wbinvd();
+ break;
+ case SLP_TYP_S4:
+ printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
+ break;
+ case SLP_TYP_S5:
+ printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
+
+ /* Disable all GPE */
+ disable_all_gpe();
+
+ /* also iterates over all bridges on bus 0 */
+ busmaster_disable_on_bus(0);
+ break;
+ default:
+ printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
+ break;
+ }
+ /* Clear pending wake status bit to avoid immediate wake */
+
+ /* Tri-state specific GPIOS to avoid leakage during S3/S5 */
+
+ /*
+ * Write back to the SLP register to cause the originally intended
+ * event again. We need to set BIT13 (SLP_EN) though to make the
+ * sleep happen.
+ */
+ enable_pm1_control(SLP_EN);
+
+ /* Make sure to stop executing code here for S3/S4/S5 */
+ if (slp_typ > 1)
+ hlt();
+
+ /*
+ * In most sleep states, the code flow of this function ends at
+ * the line above. However, if we entered sleep state S1 and wake
+ * up again, we will continue to execute code in this function.
+ */
+ reg32 = inl(ACPI_PMIO_BASE + PM1_CNT);
+ if (reg32 & SCI_EN) {
+ /* The OS is not an ACPI OS, so we set the state to S0 */
+ disable_pm1_control(SLP_EN | SLP_TYP);
+ }
+}
+
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
+static void southbridge_smi_gsmi(void)
+{
+ u32 *ret, *param;
+ uint8_t sub_command;
+
+ smi_gsmi_get_command(&sub_command, ¶m, &ret);
+ /* drivers/elog/gsmi.c */
+ *ret = gsmi_exec(sub_command, param);
+}
+#endif
+
+static void finalize(void)
+{
+ static int finalize_done;
+
+ if (finalize_done) {
+ printk(BIOS_DEBUG, "SMM already finalized.\n");
+ return;
+ }
+ finalize_done = 1;
+
+}
+
+void southbridge_smi_apmc(void)
+{
+ uint8_t reg8;
+
+ /* Emulate B2 register as the FADT / Linux expects it */
+
+ reg8 = inb(APM_CNT);
+ switch (reg8) {
+ case APM_CNT_CST_CONTROL:
+ /*
+ * Calling this function seems to cause
+ * some kind of race condition in Linux
+ * and causes a kernel oops
+ */
+ printk(BIOS_DEBUG, "C-state control\n");
+ break;
+ case APM_CNT_PST_CONTROL:
+ /*
+ * Calling this function seems to cause
+ * some kind of race condition in Linux
+ * and causes a kernel oops
+ */
+ printk(BIOS_DEBUG, "P-state control\n");
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ disable_pm1_control(SCI_EN);
+ printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
+ break;
+ case APM_CNT_ACPI_ENABLE:
+ enable_pm1_control(SCI_EN);
+ printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
+ break;
+ case APM_CNT_GNVS_UPDATE:
+ smi_update_gnvs(&gnvs);
+ break;
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
+ case ELOG_GSMI_APM_CNT:
+ southbridge_smi_gsmi();
+ break;
+#endif
+ case APM_CNT_FINALIZE:
+ finalize();
+ break;
+ }
+
+ mainboard_smi_apmc(reg8);
+}
+
+void southbridge_smi_pm1(void)
+{
+ uint16_t pm1_sts = clear_pm1_status();
+
+ /*
+ * While OSPM is not active, poweroff immediately
+ * on a power button event.
+ */
+ if (pm1_sts & PWRBTN_STS) {
+ /* power button pressed */
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
+ elog_add_event(ELOG_TYPE_POWER_BUTTON);
+#endif
+ disable_pm1_control(-1UL);
+ enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+ }
+}
+
+void southbridge_smi_gpe0(void)
+{
+ clear_gpe_status();
+}
+
+void southbridge_smi_tco(void)
+{
+ uint32_t tco_sts = clear_tco_status();
+
+ /* Any TCO event? */
+ if (!tco_sts)
+ return;
+
+ if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */
+ /* Handle TCO timeout */
+ printk(BIOS_DEBUG, "TCO Timeout.\n");
+ }
+}
+
+void southbridge_smi_periodic(void)
+{
+ uint32_t reg32;
+
+ reg32 = get_smi_en();
+
+ /* Are periodic SMIs enabled? */
+ if ((reg32 & PERIODIC_EN) == 0)
+ return;
+ printk(BIOS_DEBUG, "Periodic SMI.\n");
+}
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