[coreboot-gerrit] Patch set updated for coreboot: ec/google/chromeec/ec_lpc: Declare used IO ports as a resource

[Alexandru Gagniuc (alexandrux.gagniuc@intel.com)]

Alexandru Gagniuc (alexandrux.gagniuc at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14585

-gerrit

commit 1a234fbf0eee0b3e3cb8f32f0a515a07852c40fe
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date:   Wed Mar 30 14:38:44 2016 -0700

    ec/google/chromeec/ec_lpc: Declare used IO ports as a resource
    
    Chrome EC uses IO ports 0x800 -> 0x9ff to communicate over LPC;
    however, those ports were not declared as a resource. This had two
    major downsides:
    * It allowed the allocator to assign said ports to other devices
    * It required manually open up an IO window in the LPC bridge.
    The LPC bridge on many chromeec boards had to be painstakingly
    adjusted to meet these constraints.
    
    The advantage of declaring the resources upfront is that the lpc
    bridge can now scan its child resources and automatically open up
    IO windows, as requested by its LPC children devices.
    
    Change-Id: I35c4e48dddb7300674d7a9858b590c1f20e3b0e3
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/ec/google/chromeec/ec.h     |  4 ++++
 src/ec/google/chromeec/ec_lpc.c | 29 ++++++++++++++++++++++++++++-
 src/ec/google/chromeec/ec_mec.c |  1 -
 3 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 7f52362..85f41ad 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -59,6 +59,10 @@ int google_chromeec_vstore_info(uint32_t *locked);
 int google_chromeec_vstore_read(int slot, uint8_t *data);
 int google_chromeec_vstore_write(int slot, uint8_t *data, size_t size);
 
+/* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource. */
+#define MEC_EMI_BASE		0x800
+#define MEC_EMI_SIZE		8
+
 /* For MEC, access ranges 0x800 thru 0x9ff using EMI interface instead of LPC */
 #define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0
 #define MEC_EMI_RANGE_END   (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE)
diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c
index 021735e..f9d0f8b 100644
--- a/src/ec/google/chromeec/ec_lpc.c
+++ b/src/ec/google/chromeec/ec_lpc.c
@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <assert.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/pnp.h>
@@ -407,9 +408,35 @@ static void lpc_ec_init(struct device *dev)
 	google_chromeec_init();
 }
 
+/*
+ * Declare the IO ports that we are using:
+ *
+ * All ECs (not explicitly declared):
+ * 0x60/0x64, 0x62/0x66, 0x80, 0x200->0x207
+ *
+ * mec1322:	0x800->0x807
+ * All others:	0x800->0x9ff
+ *
+ * EC_GOOGLE_CHROMEEC_ACPI_MEMMAP is only used for MEC ECs.
+ */
 static void lpc_ec_read_resources(struct device *dev)
 {
-	/* Nothing, but this function avoids an error on serial console. */
+	unsigned int idx = 0;
+	struct resource * res;
+
+
+	res = new_resource(dev, idx++);
+	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) {
+		res->base = MEC_EMI_BASE;
+		res->size = MEC_EMI_SIZE;
+	} else {
+		res->base = EC_HOST_CMD_REGION0;
+		res->size = 2 * EC_HOST_CMD_REGION_SIZE;
+		/* Make sure MEMMAP region follows host cmd region. */
+		assert(res->base + res->size == EC_LPC_ADDR_MEMMAP);
+		res->size +=  EC_MEMMAP_SIZE;
+	}
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 static void lpc_ec_enable_resources(struct device *dev)
diff --git a/src/ec/google/chromeec/ec_mec.c b/src/ec/google/chromeec/ec_mec.c
index a9bc282..4cd0823 100644
--- a/src/ec/google/chromeec/ec_mec.c
+++ b/src/ec/google/chromeec/ec_mec.c
@@ -32,7 +32,6 @@ enum {
 };
 
 /* EMI registers are relative to base */
-#define MEC_EMI_BASE		0x800
 #define MEC_EMI_HOST_TO_EC	(MEC_EMI_BASE + 0)
 #define MEC_EMI_EC_TO_HOST	(MEC_EMI_BASE + 1)
 #define MEC_EMI_EC_ADDRESS_B0	(MEC_EMI_BASE + 2)