[coreboot-gerrit] Patch merged into coreboot/master: drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE used

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit ddf4fa0cc35e6fc65d347b8c9eb4acbe0cba51b9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Apr 29 12:43:27 2016 -0500

    drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE used
    
    The skylake-based Chromebooks use a separate verstage which runs
    just after bootblock and prior to romstage. However, that
    config is not enabled for coreboot.org so when
    C_ENVIRONMENT_BOOTBLOCK changes were done it wasn't observed
    that the Chromebook config failed because 2 _start symbols
    were present. Remedy this failure by using the common
    car_stage_entry symbol for taking over control flow.
    
    Change-Id: I3f29b90ba8e3786b2106a34e49e6d1f9831dcc7c
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/14549
    Reviewed-by: Furquan Shaikh <furquan at google.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Andrey Petrov <andrey.petrov at intel.com>
    Reviewed-by: Leroy P Leahy <leroy.p.leahy at intel.com>


See https://review.coreboot.org/14549 for details.

-gerrit