[coreboot-gerrit] New patch to review for coreboot: intel/baytrail: use fmap information for code caching

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14573

-gerrit

commit ed8c748748e172ed9d429e70d24677837ec1d31d
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Mon May 2 17:27:01 2016 +0800

    intel/baytrail: use fmap information for code caching
    
    Instead of using CBFS_SIZE from Kconfig, use values generated from fmap.
    While at it, make sure that the cached region size is a power of two.
    
    Change-Id: I03a919e1381ca3d0e972780b2c7d76c590aaa994
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 src/soc/intel/baytrail/romstage/cache_as_ram.inc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
index 9ae10af..46bcc03 100644
--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc
+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
@@ -19,6 +19,8 @@
 #include <cpu/x86/post_code.h>
 #include <cbmem.h>
 
+#include "fmap_config.h"
+
 /* The full cache-as-ram size includes the cache-as-ram portion from coreboot
  * and the space used by the reference code. These 2 values combined should
  * be a power of 2 because the MTRR setup assumes that. */
@@ -27,7 +29,7 @@
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
 /* Cache all of CBFS just below 4GiB as Write-Protect type. */
-#define CODE_CACHE_SIZE  (CONFIG_CBFS_SIZE)
+#define CODE_CACHE_SIZE  _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE)
 #define CODE_CACHE_BASE  (-CODE_CACHE_SIZE)
 #define CODE_CACHE_MASK  (~(CODE_CACHE_SIZE - 1))
 #define CPU_PHYSMASK_HI  ((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1)